| 2007 |
|---|
| 7 | EE | Daher Kaiss,
Marcelo Skaba,
Ziyad Hanna,
Zurab Khasidashvili:
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.
FMCAD 2007: 20-26 |
| 2006 |
|---|
| 6 | EE | Zurab Khasidashvili,
Marcelo Skaba,
Daher Kaiss,
Ziyad Hanna:
Post-reboot Equivalence and Compositional Verification of Hardware.
FMCAD 2006: 11-18 |
| 5 | EE | Daher Kaiss,
Silvian Goldenberg,
Zurab Khasidashvili:
Seqver : A Sequential Equivalence Verifier for Hardware Designs .
ICCD 2006 |
| 4 | EE | Nachum Dershowitz,
Jieh Hsiang,
Guan-Shieng Huang,
Daher Kaiss:
Boolean Rings for Intersection-Based Satisfiability.
LPAR 2006: 482-496 |
| 2004 |
|---|
| 3 | EE | Zurab Khasidashvili,
Marcelo Skaba,
Daher Kaiss,
Ziyad Hanna:
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.
ICCAD 2004: 58-65 |
| 2 | EE | Nachum Dershowitz,
Jieh Hsiang,
Guan-Shieng Huang,
Daher Kaiss:
Boolean Ring Satisfiability.
SAT 2004 |
| 2001 |
|---|
| 1 | EE | John Moondanos,
Carl-Johan H. Seger,
Ziyad Hanna,
Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV 2001: 131-143 |
