| 2007 |
|---|
| 8 | EE | Wolfgang Ecker,
Volkan Esen,
Lars Schönberg,
Thomas Steininger,
Michael Velten,
Michael Hull:
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.
DATE 2007: 767-772 |
| 7 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten,
Michael Hull:
Interactive presentation: Implementation of a transaction level assertion framework in SystemC.
DATE 2007: 894-899 |
| 6 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten:
Requirements and Concepts for Transaction Level Assertion Refinement.
IESS 2007: 1-14 |
| 2006 |
|---|
| 5 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten:
Case Study on Transaction Level Modeling.
FDL 2006: 209-215 |
| 4 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten,
Jacob Smit:
IP Library For Temporal SystemC Assertions.
FDL 2006: 301-309 |
| 3 | EE | Wolfgang Ecker,
Volkan Esen,
Michael Hull,
Thomas Steininger,
Michael Velten:
Requirements and Concepts for Transaction Level Assertions.
ICCD 2006 |
| 2004 |
|---|
| 2 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Martin Zambaldi:
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking.
ISORC 2004: 129-135 |
| 1 | EE | Jens Bieger,
Sorin A. Huss,
Michael Jung,
Stephan Klaus,
Thomas Steininger:
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach.
VLSI Design 2004: 577- |
