| 2009 |
|---|
| 19 | EE | Martin Dimitrov,
Huiyang Zhou:
Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging.
ASPLOS 2009: 61-72 |
| 18 | EE | Martin Dimitrov,
Mike Mantor,
Huiyang Zhou:
Understanding software approaches for GPGPU reliability.
GPGPU 2009: 94-104 |
| 17 | EE | Jingfei Kong,
Onur Aciiçmez,
Jean-Pierre Seifert,
Huiyang Zhou:
Hardware-software integrated approaches to defend against software cache-based side channel attacks.
HPCA 2009: 393-404 |
| 2008 |
|---|
| 16 | EE | Jingfei Kong,
Onur Aciiçmez,
Jean-Pierre Seifert,
Huiyang Zhou:
Deconstructing new cache designs for thwarting software cache-based side channel attacks.
CSAW 2008: 25-34 |
| 15 | EE | Hongliang Gao,
Yi Ma,
Martin Dimitrov,
Huiyang Zhou:
Address-branch correlation: A novel locality for long-latency hard-to-predict branches.
HPCA 2008: 74-85 |
| 2007 |
|---|
| 14 | EE | Martin Dimitrov,
Huiyang Zhou:
Unified Architectural Support for Soft-Error Protection or Software Bug Detection.
PACT 2007: 73-82 |
| 13 | EE | Yi Ma,
Hongliang Gao,
Martin Dimitrov,
Huiyang Zhou:
Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1080-1093 (2007) |
| 2006 |
|---|
| 12 | EE | Jingfei Kong,
Cliff Changchun Zou,
Huiyang Zhou:
Improving software security via runtime instruction-level taint checking.
ASID 2006: 18-24 |
| 11 | EE | Yi Ma,
Huiyang Zhou:
Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution.
ICCD 2006 |
| 10 | EE | Huiyang Zhou:
A case for fault tolerance and performance enhancement using chip multi-processors.
Computer Architecture Letters 5(1): 22-25 (2006) |
| 9 | EE | Yi Ma,
Hongliang Gao,
Huiyang Zhou:
Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables.
IEEE Trans. Computers 55(8): 1057-1061 (2006) |
| 2005 |
|---|
| 8 | EE | Huiyang Zhou:
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window.
IEEE PACT 2005: 231-242 |
| 7 | EE | Huiyang Zhou,
Thomas M. Conte:
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction.
IEEE Trans. Computers 54(7): 897-912 (2005) |
| 2003 |
|---|
| 6 | EE | Huiyang Zhou,
Thomas M. Conte:
Enhancing memory level parallelism via recovery-free value prediction.
ICS 2003: 326-335 |
| 5 | EE | Huiyang Zhou,
Jill Flanagan,
Thomas M. Conte:
Detecting Global Stride Locality in Value Streams.
ISCA 2003: 324-335 |
| 4 | EE | Huiyang Zhou,
Mark C. Toburen,
Eric Rotenberg,
Thomas M. Conte:
Adaptive mode control: A static-power-efficient cache design.
ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003) |
| 2002 |
|---|
| 3 | EE | Huiyang Zhou,
Thomas M. Conte:
Code Size Efficiency in Global Scheduling for ILP Processors.
Interaction between Compilers and Computer Architectures 2002: 79-90 |
| 2001 |
|---|
| 2 | EE | Huiyang Zhou,
Mark C. Toburen,
Eric Rotenberg,
Thomas M. Conte:
Adaptive Mode Control: A Static-Power-Efficient Cache Design.
IEEE PACT 2001: 61- |
| 1 | EE | Huiyang Zhou,
Matthew D. Jennings,
Thomas M. Conte:
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors.
LCPC 2001: 223-238 |
