Huiyang Zhou

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19EEMartin Dimitrov, Huiyang Zhou: Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging. ASPLOS 2009: 61-72
18EEMartin Dimitrov, Mike Mantor, Huiyang Zhou: Understanding software approaches for GPGPU reliability. GPGPU 2009: 94-104
17EEJingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou: Hardware-software integrated approaches to defend against software cache-based side channel attacks. HPCA 2009: 393-404
16EEJingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou: Deconstructing new cache designs for thwarting software cache-based side channel attacks. CSAW 2008: 25-34
15EEHongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou: Address-branch correlation: A novel locality for long-latency hard-to-predict branches. HPCA 2008: 74-85
14EEMartin Dimitrov, Huiyang Zhou: Unified Architectural Support for Soft-Error Protection or Software Bug Detection. PACT 2007: 73-82
13EEYi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou: Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery. IEEE Trans. Parallel Distrib. Syst. 18(8): 1080-1093 (2007)
12EEJingfei Kong, Cliff Changchun Zou, Huiyang Zhou: Improving software security via runtime instruction-level taint checking. ASID 2006: 18-24
11EEYi Ma, Huiyang Zhou: Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. ICCD 2006
10EEHuiyang Zhou: A case for fault tolerance and performance enhancement using chip multi-processors. Computer Architecture Letters 5(1): 22-25 (2006)
9EEYi Ma, Hongliang Gao, Huiyang Zhou: Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables. IEEE Trans. Computers 55(8): 1057-1061 (2006)
8EEHuiyang Zhou: Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. IEEE PACT 2005: 231-242
7EEHuiyang Zhou, Thomas M. Conte: Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers 54(7): 897-912 (2005)
6EEHuiyang Zhou, Thomas M. Conte: Enhancing memory level parallelism via recovery-free value prediction. ICS 2003: 326-335
5EEHuiyang Zhou, Jill Flanagan, Thomas M. Conte: Detecting Global Stride Locality in Value Streams. ISCA 2003: 324-335
4EEHuiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003)
3EEHuiyang Zhou, Thomas M. Conte: Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures 2002: 79-90
2EEHuiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-
1EEHuiyang Zhou, Matthew D. Jennings, Thomas M. Conte: Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC 2001: 223-238

Coauthor Index

1Onur Aciiçmez [16] [17]
2Thomas M. Conte [1] [2] [3] [4] [5] [6] [7]
3Martin Dimitrov [13] [14] [15] [18] [19]
4Jill Flanagan [5]
5Hongliang Gao [9] [13] [15]
6Matthew D. Jennings [1]
7Jingfei Kong [12] [16] [17]
8Yi Ma [9] [11] [13] [15]
9Mike Mantor [18]
10Eric Rotenberg [2] [4]
11Jean-Pierre Seifert [16] [17]
12Mark C. Toburen [2] [4]
13Cliff Changchun Zou [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)