2009 |
30 | EE | Yunji Chen,
Yi Lv,
Weiwu Hu,
Tianshi Chen,
Haihua Shen,
Pengyu Wang,
Hong Pan:
Fast complete memory consistency verification.
HPCA 2009: 381-392 |
29 | EE | Yunji Chen,
Tianshi Chen,
Weiwu Hu:
Global Clock, Physical Time Order and Pending Period Analysis in Multiprocessor Systems
CoRR abs/0903.4961: (2009) |
2008 |
28 | EE | Feng Zhang,
Zongren Yang,
Wei Feng,
Hao Cui,
Lingyi Huang,
Weiwu Hu:
A High Speed CMOS Transmitter and Rail-to-Rail Receiver.
DELTA 2008: 67-70 |
27 | EE | Hongbo Zeng,
Jun Wang,
Ge Zhang,
Weiwu Hu:
An interconnect-aware power efficient cache coherence protocol for CMPs.
IPDPS 2008: 1-11 |
26 | EE | Qifei Fan,
Ge Zhang,
Weiwu Hu:
A synchronized variable frequency clock scheme in chip multiprocessors.
ISCAS 2008: 3410-3413 |
2007 |
25 | EE | Hongbo Zeng,
Kun Huang,
Ming Wu,
Weiwu Hu:
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.
Asia-Pacific Computer Systems Architecture Conference 2007: 304-314 |
24 | EE | Jun Wang,
Ge Zhang,
Weiwu Hu:
An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects.
ISCAS 2007: 3712-3715 |
23 | EE | Hou Rui,
Longbing Zhang,
Weiwu Hu:
Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread.
Microprocessors and Microsystems 31(3): 200-211 (2007) |
2006 |
22 | EE | Dandan Huan,
Zusong Li,
Weiwu Hu,
Zhiyong Liu:
Processor Directed Dynamic Page Policy.
Asia-Pacific Computer Systems Architecture Conference 2006: 109-122 |
21 | EE | Hou Rui,
Longbing Zhang,
Weiwu Hu:
A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.
Euro-Par 2006: 506-516 |
20 | EE | Zusong Li,
Xianchao Xu,
Weiwu Hu,
Zhimin Tang:
Microarchitecture and Performance Analysis of Godson-2 SMT Processor.
ICCD 2006 |
19 | EE | Ge Zhang,
Weiwu Hu,
Zichu Qi:
Parallel Error Detection for Leading Zero Anticipation.
J. Comput. Sci. Technol. 21(6): 901-906 (2006) |
2005 |
18 | EE | Hou Rui,
Fuxin Zhang,
Weiwu Hu:
A Memory Bandwidth Effective Cache Store Miss Policy.
Asia-Pacific Computer Systems Architecture Conference 2005: 750-760 |
17 | EE | Ge Zhang,
Zichu Qi,
Weiwu Hu:
A novel design of leading zero anticipation circuit with parallel error detection.
ISCAS (1) 2005: 676-679 |
16 | EE | Weiwu Hu,
Fuxin Zhang,
Zusong Li:
Microarchitecture of the Godson-2 Processor.
J. Comput. Sci. Technol. 20(2): 243-249 (2005) |
2004 |
15 | EE | Gang Shi,
Mingchang Hu,
Hongda Yin,
Weiwu Hu,
Zhimin Tang:
A shared virtual memory network with fast remote direct memory access and message passing.
CLUSTER 2004: 495 |
2001 |
14 | EE | Weiwu Hu,
Gang Shi,
Fuxin Zhang:
Communication with Threads in Software DSM.
CLUSTER 2001: 149-154 |
13 | | Haiming Liu,
Weiwu Hu:
A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM.
IPDPS 2001: 62 |
12 | | Weiwu Hu,
Weisong Shi,
Zhimin Tang:
Optimizing Home-Based Software DSM Protocols.
Cluster Computing 4(3): 235-242 (2001) |
11 | EE | Weiwu Hu,
Fuxin Zhang,
Haiming Liu:
Dynamic Data Prefetching in Home-Based Software DSMs.
J. Comput. Sci. Technol. 16(3): 231-241 (2001) |
2000 |
10 | EE | Weiwu Hu,
Fuxin Zhang,
Haiming Liu:
A New Home-Based Software DSM Protocol for SMP Clusters.
Euro-Par 2000: 1132-1142 |
1999 |
9 | EE | Weiwu Hu,
Weisong Shi,
Zhimin Tang:
Write Detection in Home-Based Software DSMs.
Euro-Par 1999: 909-913 |
8 | EE | M. Rasit Eskicioglu,
T. Anthony Marsland,
Weiwu Hu,
Weisong Shi:
Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures.
HICSS 1999 |
7 | | Weiwu Hu,
Weisong Shi,
Zhimin Tang:
JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol.
HPCN Europe 1999: 463-472 |
6 | EE | Weiwu Hu,
Weisong Shi,
Zhimin Tang:
Adaptive Write Detection in Home-based Software DSMs.
HPDC 1999 |
5 | EE | Weisong Shi,
Weiwu Hu,
Zhimin Tang,
M. Rasit Eskicioglu:
Dynamic Task Migration in Home-based Software DSM Systems.
HPDC 1999 |
4 | EE | Weiwu Hu,
Weisong Shi,
Zhimin Tang:
Reducing System Overheads in Home-based Software DSMs.
IPPS/SPDP 1999: 167- |
1997 |
3 | | Weisong Shi,
Weiwu Hu,
Zhimin Tang:
An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems.
Operating Systems Review 31.(4): 41-54 (1997) |
1996 |
2 | EE | Weiwu Hu,
Peisu Xia:
Event Ordering Condition for Correct Executions in Shared-Memory Systems.
ISPAN 1996: 84-89 |
1994 |
1 | | Weiwu Hu:
A Graph Model for Investigating Memory Consistency.
ICPADS 1994: 516-523 |