| 2008 |
|---|
| 69 | EE | Kangtao Kendall Chuang,
Sudhakar Yalamanchili,
Ada Gavrilovska,
Karsten Schwan:
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.
FCCM 2008: 265-268 |
| 68 | EE | Gregory F. Diamos,
Sudhakar Yalamanchili:
Harmony: an execution model and runtime for heterogeneous many core systems.
HPDC 2008: 197-200 |
| 67 | EE | Subramanian Ramaswamy,
Sudhakar Yalamanchili:
An Utilization Driven Framework for Energy Efficient Caches.
HiPC 2008: 583-594 |
| 2007 |
|---|
| 66 | EE | Subramanian Ramaswamy,
Sudhakar Yalamanchili:
Customized Placement for High Performance Embedded Processor Caches.
ARCS 2007: 69-82 |
| 65 | EE | Subramanian Ramaswamy,
Sudhakar Yalamanchili:
Improving cache efficiency via resizing + remapping.
ICCD 2007: 47-54 |
| 2006 |
|---|
| 64 | EE | Subramanian Ramaswamy,
Sudhakar Yalamanchili:
Customizable Fault Tolerant Caches for Embedded Processors.
ICCD 2006 |
| 63 | EE | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
MMR: A MultiMedia Router architecture to support hybrid workloads.
J. Parallel Distrib. Comput. 66(2): 307-321 (2006) |
| 2005 |
|---|
| 62 | EE | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router.
IEEE Trans. Parallel Distrib. Syst. 16(11): 1009-1021 (2005) |
| 2004 |
|---|
| 61 | EE | Krishna V. Palem,
Lakshmi N. Chakrapani,
Sudhakar Yalamanchili:
A Framework for Compiler Driven Design Space Exploration for Embedded System Customization.
ASIAN 2004: 395-406 |
| 60 | EE | Raj Krishnamurthy,
Sudhakar Yalamanchili,
Karsten Schwan,
Richard West:
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers.
FCCM 2004: 115-124 |
| 2003 |
|---|
| 59 | EE | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR.
IPDPS 2003: 197 |
| 58 | EE | Raj Krishnamurthy,
Sudhakar Yalamanchili,
Karsten Schwan,
Richard West:
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture.
IPDPS 2003: 30 |
| 57 | | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR.
PDPTA 2003: 220-226 |
| 2002 |
|---|
| 56 | EE | Indrani Paul,
Sudhakar Yalamanchili,
José Duato:
Algorithms for Switch-Scheduling in the Multimedia Router for LANs.
HiPC 2002: 219-231 |
| 55 | EE | Sudhakar Yalamanchili:
The Customization Landscape for Embedded Systems.
HiPC 2002: 693-696 |
| 54 | EE | Raj Krishnamurthy,
Sudhakar Yalamanchili,
Karsten Schwan,
Richard West:
Architecture and Hardware for Scheduling Gigabit Packet Streams.
Hot Interconnects 2002: 52-64 |
| 53 | | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
A new switch scheduling algorithm to improve QoS in the multimedia router.
IEEE Workshop on Multimedia Signal Processing 2002: 376-379 |
| 52 | EE | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router.
IPDPS 2002 |
| 51 | | Craig Ulmer,
Sudhakar Yalamanchili:
A Tunable Communications Library for Data Injection.
PDPTA 2002: 1630-1636 |
| 2001 |
|---|
| 50 | EE | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR).
ICN (2) 2001: 358-369 |
| 49 | | Blanca Caminero,
Carmen Carrión,
Francisco J. Quiles,
José Duato,
Sudhakar Yalamanchili:
Tuning Buffer Size in the Multimedia Router (MMR).
IPDPS 2001: 160 |
| 2000 |
|---|
| 48 | EE | Damon S. Love,
Sudhakar Yalamanchili,
José Duato,
Blanca Caminero,
Francisco J. Quiles:
Switch Scheduling in the Multimedia Router (MMR).
IPDPS 2000: 5-12 |
| 47 | | Craig Ulmer,
Sudhakar Yalamanchili:
An Extensible Message Layer for High-Performance Clusters.
PDPTA 2000 |
| 46 | EE | Young-Joo Suh,
Binh Vien Dao,
José Duato,
Sudhakar Yalamanchili:
Software-Based Rerouting for Fault-Tolerant Pipelined Communication.
IEEE Trans. Parallel Distrib. Syst. 11(3): 193-211 (2000) |
| 45 | EE | Young-Joo Suh,
Sudhakar Yalamanchili:
Configurable Algorithms for Complete Exchange in 2D Meshes.
IEEE Trans. Parallel Distrib. Syst. 11(4): 337-356 (2000) |
| 1999 |
|---|
| 44 | | Blanca Caminero,
Francisco J. Quiles,
José Duato,
Damon S. Love,
Sudhakar Yalamanchili:
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic.
CANPC 1999: 62-76 |
| 43 | EE | José Duato,
Sudhakar Yalamanchili,
Blanca Caminero,
Damon S. Love,
Francisco J. Quiles:
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs.
HPCA 1999: 300-309 |
| 42 | EE | Richard West,
Raj Krishnamurthy,
W. K. Norton,
Karsten Schwan,
Sudhakar Yalamanchili,
Marcel-Catalin Rosu,
V. Sarat:
QUIC: A Quality of Service Network Interface Layer for Communication in NOWs.
Heterogeneous Computing Workshop 1999: 199-208 |
| 41 | EE | Tsai Chi Huang,
Sudhakar Yalamanchili,
Roy W. Melton,
Philip R. Bingham,
Cecil O. Alford:
Teaching Pipelining and Concurrency using Hardware Description Languages.
MSE 1999: 55-56 |
| 40 | EE | Binh Vien Dao,
José Duato,
Sudhakar Yalamanchili:
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing.
IEEE Trans. Parallel Distrib. Syst. 10(1): 7-22 (1999) |
| 1998 |
|---|
| 39 | | Sudhakar Yalamanchili,
José Duato:
Parallel Computer Routing and Communication, Second International Workshop, PCRCW'97, Atlanta, Georgia, USA, June 26-27, 1997, Proceedings
Springer 1998 |
| 38 | EE | Daniela Rosu,
Karsten Schwan,
Sudhakar Yalamanchili:
FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems.
IEEE Real Time Technology and Applications Symposium 1998: 79-84 |
| 37 | EE | Young-Joo Suh,
Sudhakar Yalamanchili:
All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes.
IEEE Trans. Parallel Distrib. Syst. 9(5): 442-458 (1998) |
| 1997 |
|---|
| 36 | EE | Binh Vien Dao,
Sudhakar Yalamanchili,
José Duato:
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks.
HPCA 1997: 343-352 |
| 35 | | Chirag S. Patel,
Sek M. Chai,
Sudhakar Yalamanchili,
David E. Schimmel:
Power Constrained Design of Multiprocessor Interconnection Networks.
ICCD 1997: 408-416 |
| 34 | EE | Daniela Rosu,
Karsten Schwan,
Sudhakar Yalamanchili,
Rakesh Jha:
On adaptive resource allocation for complex real-time application.
IEEE Real-Time Systems Symposium 1997: 320-329 |
| 33 | EE | José Duato,
Pedro López,
Sudhakar Yalamanchili:
Deadlock- and Livelock-Free Routing Protocols for Wave Switching.
IPPS 1997: 570-577 |
| 32 | EE | Chirag S. Patel,
Sek M. Chai,
Sudhakar Yalamanchili,
David E. Schimmel:
Power/Performance Trade-offs for Direct Networks.
PCRCW 1997: 231-246 |
| 1996 |
|---|
| 31 | | José Duato,
Pedro López,
Federico Silla,
Sudhakar Yalamanchili:
A High Performance Router Architecture for Interconnection Networks.
ICPP, Vol. 1 1996: 61-68 |
| 30 | EE | Young-Joo Suh,
Sudhakar Yalamanchili:
Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori.
IPPS 1996: 808-814 |
| 29 | | Patrick T. Gaughan,
Binh Vien Dao,
Sudhakar Yalamanchili,
David E. Schimmel:
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks.
IEEE Trans. Computers 45(6): 651-665 (1996) |
| 28 | | Hari Lalgudi,
Ian F. Akyildiz,
Sudhakar Yalamanchili:
Augmented Binary Hypercube: A New Architecture for Processor Management.
IEEE Trans. Computers 45(8): 980-984 (1996) |
| 27 | | Sudhakar Yalamanchili,
Todd Carpenter:
Paradigms for Modeling and Simulation of Multiprocessor Architectures.
Int. Journal in Computer Simulation 6(1): 137- (1996) |
| 1995 |
|---|
| 26 | | Young-Joo Suh,
Binh Vien Dao,
José Duato,
Sudhakar Yalamanchili:
Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks.
ICPP (1) 1995: 101-105 |
| 25 | EE | Hatem Sellami,
Sudhakar Yalamanchili:
Time scale combining of conservative parallel discrete event simulations.
IPPS 1995: 599- |
| 24 | EE | Binh Vien Dao,
José Duato,
Sudhakar Yalamanchili:
Configurable Flow Control Mechanisms for Fault-Tolerant Routing.
ISCA 1995: 220-229 |
| 23 | EE | Hatem Sellami,
Sudhakar Yalamanchili:
Parallelism in Sequential Multiprocessor Simulation Models: A Case Study.
ACM Trans. Model. Comput. Simul. 5(2): 101-128 (1995) |
| 22 | EE | Sudhakar Yalamanchili,
Lynn E. Te Winkel,
David L. Perschbacher,
Belle Shenoy:
Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints.
Concurrency - Practice and Experience 7(3): 167-189 (1995) |
| 21 | | Patrick T. Gaughan,
Sudhakar Yalamanchili:
A Performance Model of Pipelined K-ary n-cubes.
IEEE Trans. Computers 44(8): 1059-1063 (1995) |
| 20 | EE | Patrick T. Gaughan,
Sudhakar Yalamanchili:
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks.
IEEE Trans. Parallel Distrib. Syst. 6(5): 482-497 (1995) |
| 1994 |
|---|
| 19 | | José Duato,
V. B. Dao,
Patrick T. Gaughan,
Sudhakar Yalamanchili:
Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks.
ICPADS 1994: 608-613 |
| 18 | | James D. Allen,
Patrick T. Gaughan,
David E. Schimmel,
Sudhakar Yalamanchili:
Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers.
ISCA 1994: 278-288 |
| 17 | | Hatem Sellami,
James D. Allen,
David E. Schimmel,
Sudhakar Yalamanchili:
Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management.
MASCOTS 1994: 343-348 |
| 16 | EE | Eileen Tien Lin,
Edward Omiecinski,
Sudhakar Yalamanchili:
Large Join Optimization on a Hypercube Multiprocessor.
IEEE Trans. Knowl. Data Eng. 6(2): 304-315 (1994) |
| 15 | | Christopher H. de Castro,
Sudhakar Yalamanchili:
Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures.
Int. Journal in Computer Simulation 4(4): 0- (1994) |
| 1993 |
|---|
| 14 | | Patrick T. Gaughan,
Sudhakar Yalamanchili:
Analytical Models of Bandwidth Allocation in Pipelined k-ary n-cubes.
IPPS 1993: 395-400 |
| 13 | | Hatem Sellami,
Sudhakar Yalamanchili:
Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models.
SPDP 1993: 360-367 |
| 12 | | Sudhakar Yalamanchili,
Lynn E. Te Winkel,
David L. Perschbacher,
Belle Shenoy:
Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors.
SPDP 1993: 522-529 |
| 11 | | Patrick T. Gaughan,
Sudhakar Yalamanchili:
Adaptive Routing Protocols for Hypercube Interconnection Networks.
IEEE Computer 26(5): 12-23 (1993) |
| 1992 |
|---|
| 10 | | Eileen Tien Lin,
Edward Omiecinski,
Sudhakar Yalamanchili:
Parallel Optimization and Execution of Large Join Queries.
FGCS 1992: 907-914 |
| 9 | | Ajay Mohindra,
Sudhakar Yalamanchili:
Dominant Representations: A Paradigm for Mapping Parallel Computations.
IPPS 1992: 67-71 |
| 8 | | Patrick T. Gaughan,
Sudhakar Yalamanchili:
Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing.
SPDP 1992: 148-155 |
| 1987 |
|---|
| 7 | | Sudhakar Yalamanchili,
Jake K. Aggarwal:
A Characterization and Analysis of Parallel Processor Interconnection Networks.
IEEE Trans. Computers 36(6): 680-691 (1987) |
| 6 | EE | S. Y. Lee,
Sudhakar Yalamanchili,
Jake K. Aggarwal:
Parallel image normalization on a mesh connected array processor.
Pattern Recognition 20(1): 115-124 (1987) |
| 1985 |
|---|
| 5 | | Sudhakar Yalamanchili,
Jake K. Aggarwal:
Reconfiguration Strategies for Parallel Architectures.
IEEE Computer 18(12): 44-61 (1985) |
| 4 | EE | Sudhakar Yalamanchili,
Jake K. Aggarwal:
Analysis of a model for parallel image processing.
Pattern Recognition 18(1): 1-16 (1985) |
| 3 | EE | Sudhakar Yalamanchili,
Jake K. Aggarwal:
A system organization for parallel image processing.
Pattern Recognition 18(1): 17-29 (1985) |
| 1984 |
|---|
| 2 | EE | Sudhakar Yalamanchili,
Jake K. Aggarwal:
Algebraic Properties of some Parallel Processor Interconnection Networks.
ICDE 1984: 611-618 |
| 1 | | Sudhakar Yalamanchili,
Miroslaw Malek,
Jake K. Aggarwal:
Workstations in a Local Area Network Environment.
IEEE Computer 17(11): 74-86 (1984) |
