| 2009 |
|---|
| 10 | EE | Debasish Das,
William Scott,
Shahin Nazarian,
Hai Zhou:
An efficient current-based logic cell model for crosstalk delay analysis.
ISQED 2009: 627-633 |
| 2008 |
|---|
| 9 | EE | Debasish Das,
Kip Killpack,
Chandramouli V. Kashyap,
Abhijit Jas,
Hai Zhou:
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.
ASP-DAC 2008: 486-491 |
| 2007 |
|---|
| 8 | EE | Debasish Das,
Ahmed Shebaita,
Yehea I. Ismail,
Hai Zhou,
Kip Killpack:
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
ACM Great Lakes Symposium on VLSI 2007: 25-30 |
| 7 | EE | Jia Wang,
Debasish Das,
Hai Zhou:
Gate sizing by Lagrangian relaxation revisited.
ICCAD 2007: 111-118 |
| 2006 |
|---|
| 6 | EE | Debasish Das,
Ahmed Shebaita,
Hai Zhou,
Yehea I. Ismail,
Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
ICCD 2006 |
| 2005 |
|---|
| 5 | EE | Somsubhra Mondal,
Seda Ogrenci Memik,
Debasish Das:
Hierarchical LUT structures for leakage power reduction (abstract only).
FPGA 2005: 272 |
| 1999 |
|---|
| 4 | | Debasish Das,
Mallika De,
Bhabani P. Sinha:
A New Network Topology with Multiple Meshes.
IEEE Trans. Computers 48(5): 536-551 (1999) |
| 1997 |
|---|
| 3 | | Mallika De,
Debasish Das,
Mabhin Ghosh,
Bhabani P. Sinha:
An Efficient Sorting Algorithm on the Multi-Mesh Network.
IEEE Trans. Computers 46(10): 1132-1136 (1997) |
| 1995 |
|---|
| 2 | EE | Debasish Das,
Bhabani P. Sinha:
Multi-Mesh-an efficient topology for parallel processing.
IPPS 1995: 17-21 |
| 1 | | Debasish Das,
Krishnendu Mukhopadhyaya,
Bhabani P. Sinha:
Implementation of Four Common Functions on an LNS Co-Processor.
IEEE Trans. Computers 44(1): 155-161 (1995) |
