| 2008 |
|---|
| 6 | EE | Zhiyi Yu,
Bevan M. Baas:
A low-area interconnect architecture for chip multiprocessors.
ISCAS 2008: 2857-2860 |
| 5 | EE | Zhiyi Yu,
Michael J. Meeuwsen,
Ryan W. Apperson,
Omar Sattari,
Michael A. Lai,
Jeremy W. Webb,
Eric W. Work,
Tinoosh Mohsenin,
Bevan M. Baas:
Architecture and Evaluation of an Asynchronous Array of Simple Processors.
Signal Processing Systems 53(3): 243-259 (2008) |
| 2007 |
|---|
| 4 | EE | Bevan M. Baas,
Zhiyi Yu,
Michael J. Meeuwsen,
Omar Sattari,
Ryan W. Apperson,
Eric W. Work,
Jeremy W. Webb,
Michael A. Lai,
Tinoosh Mohsenin,
Dean Truong,
Jason Cheung:
AsAP: A Fine-Grained Many-Core Platform for DSP Applications.
IEEE Micro 27(2): 34-45 (2007) |
| 3 | EE | Ryan W. Apperson,
Zhiyi Yu,
Michael J. Meeuwsen,
Tinoosh Mohsenin,
Bevan M. Baas:
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. VLSI Syst. 15(10): 1125-1134 (2007) |
| 2006 |
|---|
| 2 | EE | Zhiyi Yu,
Bevan M. Baas:
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
ICCD 2006 |
| 1 | EE | Zhiyi Yu,
Bevan M. Baas:
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.
ISVLSI 2006: 378-383 |
