| 2006 |
|---|
| 10 | EE | Jinwen Xi,
Peixin Zhong:
A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.
ACM Great Lakes Symposium on VLSI 2006: 341-344 |
| 9 | EE | Jinwen Xi,
Peixin Zhong:
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models.
ICCD 2006 |
| 2005 |
|---|
| 8 | | Zhaohui Huang,
Peixin Zhong:
Adaptive Analog-to-Digital Converter Platform for Mixed-Signal System-on-Chip.
ESA 2005: 69-73 |
| 7 | | Jinwen Xi,
Peixin Zhong:
Fast Energy Estimation of Multi-processor System-on-Chip with Energy Macro-Models for Embedded Microprocessors.
MSV 2005: 107-111 |
| 2004 |
|---|
| 6 | EE | Zhaohui Huang,
Peixin Zhong:
An Architectural Power Estimator for Analog-to-Digital Converters.
ICCD 2004: 397-400 |
| 5 | EE | Jinwen Xi,
Peixin Zhong:
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC.
ICCD 2004: 502-504 |
| 1999 |
|---|
| 4 | EE | Peixin Zhong,
Margaret Martonosi,
Pranav Ashar,
Sharad Malik:
Using configurable computing to accelerate Boolean satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 861-868 (1999) |
| 1998 |
|---|
| 3 | EE | Peixin Zhong,
Pranav Ashar,
Sharad Malik,
Margaret Martonosi:
Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability.
DAC 1998: 194-199 |
| 2 | EE | Peixin Zhong,
Margaret Martonosi,
Pranav Ashar,
Sharad Malik:
Accelerating Boolean Satisfiability with Configurable Hardware.
FCCM 1998: 186-195 |
| 1 | EE | Peixin Zhong,
Margaret Martonosi,
Pranav Ashar,
Sharad Malik:
Solving Boolean Satisfiability with Dynamic Hardware Configurations.
FPL 1998: 326-335 |
