Mauricio Breternitz Jr.

2007
15	EE	Cheng Wang, Shiliang Hu, Ho-Seop Kim, Sreekumar R. Nair, Mauricio Breternitz Jr., Zhiwei Ying, Youfeng Wu: StarDBT: An Efficient Multi-platform Dynamic Binary Translation System. Asia-Pacific Computer Systems Architecture Conference 2007: 4-15
14	EE	Youfeng Wu, Mauricio Breternitz Jr., Victor Ying: Impacts of Multiprocessor Configurations on Workloads in Bioinformatics. SBAC-PAD 2007: 105-113
2006
13	EE	Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, Guido Araujo: Clustering-Based Microcode Compression. ICCD 2006
2005
12	EE	Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett: Enhanced code density of embedded CISC processors with echo technology. CODES+ISSS 2005: 160-165
2004
11	EE	Youfeng Wu, Mauricio Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang: The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators. CGO 2004: 227-238
10	EE	Youfeng Wu, Mauricio Breternitz Jr., Tevi Devor: Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translato. Interaction between Compilers and Computer Architectures 2004: 3-12
2003
9	EE	Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjeev Kumar: Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU. IEEE PACT 2003: 135-
1997
8		Mauricio Breternitz Jr., Roger Smith: Enhanced Compression Techniques to Simplify Programm Decompression and Execution. ICCD 1997: 170-176
1996
7		Tariq Afzal, Mauricio Breternitz Jr., M. Kacher, S. Menyhert, M. Ommerman, W. Su: Motorola PowerPC Migration Tools - Emulation and Translation. COMPCON 1996: 145-150
6	EE	Mauricio Breternitz Jr., A. Manikonda, M. Ommerman, W. Su, A. Thornto: Design Tradeoffs and Experience with Motorola PowerPC? Migration Tool. ICCD 1996: 301-
1994
5		Barbara Simons, Vivek Sarkar, Mauricio Breternitz Jr., Michael Lai: An Optimal Asynchronous Scheduling Algorithm for Software Cache Consistence. HICSS (2) 1994: 502-511
1991
4	EE	Mauricio Breternitz Jr., John Paul Shen: Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. MICRO 1991: 114-123
1990
3	EE	Mauricio Breternitz Jr., John Paul Shen: Architecture Synthesis of High-Performance Application-Specific Processors. DAC 1990: 542-548
1988
2		Andrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen: The White Dwarf: A High-Performance Application-Specific Processor. ISCA 1988: 212-222
1	EE	Mauricio Breternitz Jr., John Paul Shen: Organization of array data for concurrent memory access. MICRO 1988: 97-99

Coauthor Index

1	Tariq Afzal	[7]
2	Guido Araujo	[13]
3	Ronald P. Bianchini Jr.	[2]
4	Edson Borin	[13]
5	Tevi Devor	[10]
6	Orna Etzion	[11]
7	Jesse Fang	[11]
8	Shiliang Hu	[15]
9	Herbert H. J. Hum	[9] [12]
10	M. Kacher	[7]
11	Ho-Seop Kim	[15]
12	D. B. Kirk	[2]
13	Sanjeev Kumar	[9]
14	Michael Lai	[5]
15	A. Manikonda	[6]
16	S. Menyhert	[7]
17	Sreekumar R. Nair	[15]
18	M. Ommerman	[6] [7]
19	Ramesh V. Peri	[12]
20	Jay Pickett	[12]
21	Justin Quek	[11]
22	Vivek Sarkar	[5]
23	John Paul Shen	[1] [2] [3] [4]
24	Barbara B. Simons (Barbara Simons)	[5]
25	Roger Smith	[8]
26	Chriss Stephens	[2]
27	W. Su	[6] [7]
28	A. Thornto	[6]
29	A. L. Ting	[2]
30	Cheng Wang	[15]
31	Andrew Wolfe	[2]
32	Youfeng Wu	[10] [11] [12] [13] [14] [15]
33	Victor Ying	[14]
34	Zhiwei Ying	[15]

Colors in the list of coauthors