Dan Connors
List of publications from the DBLP Bibliography Server - FAQ
2009 | ||
---|---|---|
33 | EE | Alex Shye, Joseph Blomstedt, Tipp Moseley, Vijay Janapa Reddi, Daniel A. Connors: PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures. IEEE Trans. Dependable Sec. Comput. 6(2): 135-148 (2009) |
2008 | ||
32 | EE | Justin Emile Gottschlich, Daniel A. Connors: Optimizing consistency checking for memory-intensive transactions. PODC 2008: 451 |
2007 | ||
31 | EE | Dan Fay, Alex Shye, Sayantan Bhattacharya, Daniel A. Connors, Steve Wichmann: An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment. AHS 2007: 250-257 |
30 | EE | Vijay Janapa Reddi, Dan Connors, Robert Cohn, Michael D. Smith: Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications. CGO 2007: 74-88 |
29 | EE | Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri: Identifying potential parallelism via loop-centric profiling. Conf. Computing Frontiers 2007: 143-152 |
28 | EE | Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors: Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance. DSN 2007: 297-306 |
27 | EE | Joshua L. Kihm, Samuel D. Strom, Daniel A. Connors: Phase-Guided Small-Sample Simulation. ISPASS 2007: 84-93 |
2006 | ||
26 | EE | David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors: Exploiting parallelism and structure to accelerate the simulation of chip multi-processors. HPCA 2006: 29-40 |
25 | EE | Hassan Al-Sukhni, James Holt, Daniel A. Connors: Improved stride prefetching using extrinsic stream characteristics. ISPASS 2006: 166-176 |
24 | EE | Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks: Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. IEEE Micro 26(1): 119-129 (2006) |
23 | EE | Alex Settle, Dan Connors, Enric Gibert, Antonio González: A dynamically reconfigurable cache for multithreaded processors. J. Embedded Computing 2(2): 221-233 (2006) |
2005 | ||
22 | EE | Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Daniel A. Connors: Code coverage testing using hardware performance monitoring support. AADEBUG 2005: 159-163 |
21 | EE | Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, David Hodgdon, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors: Dynamic run-time architecture techniques for enabling continuous optimization. Conf. Computing Frontiers 2005: 211-220 |
20 | EE | Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors: Methods for Modeling Resource Contention on Simultaneous Multithreading Processors. ICCD 2005: 373-380 |
19 | EE | Matthew Ouellette, Daniel A. Connors: Analysis of Hardware Acceleration in Reconfigurable Embedded Systems. IPDPS 2005 |
18 | EE | Joshua L. Kihm, Daniel A. Connors: Statistical Simulation of Multithreaded Architectures. MASCOTS 2005: 67-74 |
17 | EE | Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks: A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. MICRO 2005: 271-282 |
16 | EE | Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors: Chip multi-processor scalability for single-threaded applications. SIGARCH Computer Architecture News 33(4): 44-53 (2005) |
2004 | ||
15 | EE | Joshua L. Kihm, Daniel A. Connors: Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. ICCD 2004: 326-331 |
14 | EE | Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors: Architectural Support for Enhanced SMT Job Scheduling. IEEE PACT 2004: 63-73 |
13 | S. P. Muszala, Gita Alaghband, Daniel A. Connors, James J. Hack: A VFSA Scheduler for Radiative Transfer Data in Climate Models. ISCA PDCS 2004: 64-71 | |
2003 | ||
12 | EE | Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery: Optimization for the Intel® Itanium ®Architectur Register Stack. CGO 2003: 115-124 |
11 | EE | Andreas Hagen, Daniel A. Connors, Bryan L. Pellom: The analysis and design of architecture systems for speech recognition on modern handheld-computing devices. CODES+ISSS 2003: 65-70 |
10 | EE | Hassan Al-Sukhni, Ian Bratt, Daniel A. Connors: Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures. IEEE PACT 2003: 91- |
9 | EE | Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel A. Connors: Compiler-Directed Resource Management for Active Code Regions. Interaction between Compilers and Computer Architectures 2003: 85-94 |
2000 | ||
8 | EE | Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu: Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse. ASPLOS 2000: 222-233 |
1999 | ||
7 | EE | Daniel A. Connors, Jean-Michel Puiatti, David I. August, Kevin M. Crozier, Wen-mei W. Hwu: An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors. Euro-Par 1999: 1301-1311 |
6 | EE | David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu: The Program Decision Logic Approach to Predicated Execution. ISCA 1999: 208-219 |
5 | EE | Daniel A. Connors, Wen-mei W. Hwu: Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. MICRO 1999: 158-169 |
4 | EE | Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu: Run-Time Cache Bypassing. IEEE Trans. Computers 48(12): 1338-1354 (1999) |
1998 | ||
3 | EE | David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu: Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture. ISCA 1998: 227-237 |
2 | EE | Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu: Compiler-Directed Early Load-Address Generation. MICRO 1998: 138-147 |
1997 | ||
1 | EE | David I. August, Daniel A. Connors, John C. Gyllenhaal, Wen-mei W. Hwu: Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results. HPCA 1997: 84-93 |