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Intel Santa Clara, California
List of publications from the DBLP Bibliography Server - FAQother persons with the same name:
2009 | ||
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30 | EE | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Blliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang: Intel® atomTM processor core made FPGA-synthesizable. FPGA 2009: 209-218 |
29 | EE | Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh: Criticality-based optimizations for efficient load processing. HPCA 2009: 419-430 |
2008 | ||
28 | EE | Michael D. Linderman, Jamison D. Collins, Hong Wang, Teresa H. Y. Meng: Merge: a programming model for heterogeneous multi-core systems. ASPLOS 2008: 287-296 |
27 | EE | Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz: Processor Performance Modeling using Symbolic Simulation. ISPASS 2008: 127-138 |
26 | EE | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang: Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT 2008: 52-61 |
25 | EE | Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen: Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distrib. Syst. 19(7): 914-925 (2008) |
2007 | ||
24 | EE | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang: Sequencer virtualization. ICS 2007: 148-157 |
23 | EE | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang: EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. PLDI 2007: 156-166 |
2006 | ||
22 | EE | Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John Paul Shen: Multiple Instruction Stream Processor. ISCA 2006: 114-127 |
2005 | ||
21 | EE | Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder: A Dependency Chain Clustered Microarchitecture. IPDPS 2005 |
2004 | ||
20 | EE | Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen: Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. ASPLOS 2004: 144-155 |
19 | EE | Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen: Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. CGO 2004: 27-38 |
18 | EE | Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen: Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95 |
17 | EE | Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang: Best of Both Latency and Throughput. ICCD 2004: 236-243 |
16 | EE | Jamison D. Collins, Dean M. Tullsen, Hong Wang: Control Flow Optimization Via Dynamic Reconvergence Prediction. MICRO 2004: 129-140 |
15 | EE | Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen: Helper Threads via Virtual Multithreading. IEEE Micro 24(6): 74-82 (2004) |
2003 | ||
14 | EE | Hong Wang, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt: Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. ISPASS 2003: 11-21 |
13 | EE | Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen: A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 |
2002 | ||
12 | EE | Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen: Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA 2002: 187-196 |
11 | EE | R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen: Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Interaction between Compilers and Computer Architectures 2002: 57-67 |
10 | EE | Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery: Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. PLDI 2002: 117-128 |
2001 | ||
9 | EE | Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen: Register Renaming and Scheduling for Dynamic Execution of Predicated Code. HPCA 2001: 15-26 |
8 | EE | Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen: Speculative precomputation: long-range prefetching of delinquent loads. ISCA 2001: 14-25 |
7 | EE | Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen: Dynamic speculative precomputation. MICRO 2001: 306-317 |
2000 | ||
6 | EE | Thomas Y. Yeh, Hong Wang: Redundant Arithmetic Optimizations (Research Note). Euro-Par 2000: 984-988 |
1997 | ||
5 | Hong Wang, Tong Sun, Qing Yang: Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. IEEE Trans. Computers 46(11): 1187-1201 (1997) | |
1995 | ||
4 | EE | Hong Wang, Tong Sun, Qing Yang: CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. ISCA 1995: 381-390 |
1993 | ||
3 | EE | Qing Yang, Hong Wang: A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 4(10): 1165-1171 (1993) |
1992 | ||
2 | Qing Yang, Hong Wang: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. ICPP (1) 1992: 253-256 | |
1991 | ||
1 | Hong Wang, Qing Yang: Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. ICPP (1) 1991: 25-32 |