| 2005 |
|---|
| 28 | EE | Thumrongsak Kosiyatrakul,
Susan Older,
Shiu-Kai Chin:
A Modal Logic for Role-Based Access Control.
MMM-ACNS 2005: 179-193 |
| 2003 |
|---|
| 27 | EE | Thumrongsak Kosiyatrakul,
Susan Older,
Polar Humenn,
Shiu-Kai Chin:
Implementing a Calculus for Distributed Access Control in Higher Order Logic and HOL.
MMM-ACNS 2003: 32-46 |
| 26 | | Susan Older,
Shiu-Kai Chin:
Outcomes-based Assessment as an Assurance Education Tool.
World Conference on Information Security Education 2003: 179-196 |
| 2002 |
|---|
| 25 | EE | Susan Older,
Shiu-Kai Chin:
Formal Methods for Assuring Security of Protocols.
Comput. J. 45(1): 46-54 (2002) |
| 1999 |
|---|
| 24 | EE | Sae Hwan Kim,
Shiu-Kai Chin:
Formal Verification of Tree-Structured Carry-Lookahead Adders.
Great Lakes Symposium on VLSI 1999: 232-233 |
| 23 | EE | Dan Zhou,
Joncheng C. Kuo,
Susan Older,
Shiu-Kai Chin:
Formal Development of Secure Email.
HICSS 1999 |
| 22 | EE | Dan Zhou,
Shiu-Kai Chin:
Formal Analysis of a Secure Communication Channel: Secure Core-Email Protocol.
World Congress on Formal Methods 1999: 758-775 |
| 21 | EE | Shiu-Kai Chin:
High-Confidence Design for Security: Don't Trust - Verify.
Commun. ACM 42(7): 33-37 (1999) |
| 1998 |
|---|
| 20 | EE | Shiu-Kai Chin,
Jang Dae Kim:
An Instruction Set Process Calculus.
FMCAD 1998: 451-468 |
| 19 | | Cynthia E. Irvine,
Shiu-Kai Chin,
Deborah A. Frincke:
Integrating Security into the Curriculum.
IEEE Computer 31(12): 25-30 (1998) |
| 1996 |
|---|
| 18 | EE | Shiu-Kai Chin,
John Faust,
Joseph Giordano:
Formal Methods Applied to Secure Network Engineering.
ICECCS 1996: 344-351 |
| 17 | EE | Juin-Yeu Joseph Lu,
Jang Dae Kim,
Shiu-Kai Chin:
Hardware Composition with Hardware Flowcharts and Process Algebras.
ICECCS 1996: 352- |
| 16 | EE | Milica Barjaktarovic,
Shiu-Kai Chin,
Kamal Jabbour:
Formal Specification and Verification of the Kernel Functional Unit of the OSI Session Layer Protocol and Service Using CCS.
ISSTA 1996: 270-279 |
| 1995 |
|---|
| 15 | EE | Anand Chavan,
Shiu-Kai Chin,
Shahid Ikram,
Jang Dae Kim,
Juin-Yeu Zu:
Extending VLSI design with higher-order logic.
ICCD 1995: 85- |
| 14 | EE | Milica Barjaktarovic,
Shiu-Kai Chin,
Kamal Jabbour:
Formal specification and verification of communication protocols using automated tools .
ICECCS 1995: 246-253 |
| 13 | EE | Shiu-Kai Chin,
John Faust,
Joseph Giordano:
Integrating formal methods tools to support system design.
ICECCS 1995: 88- |
| 12 | | Jang Dae Kim,
Shiu-Kai Chin:
Formal Verification of Serial Pipeline Multipliers.
TPHOLs 1995: 229-244 |
| 1994 |
|---|
| 11 | | Yegnashankar Parasuram,
Edward P. Stabler,
Shiu-Kai Chin:
Parallel implementation of BDD Algorithms using a Distributed Shared Memory.
HICSS (1) 1994: 16-25 |
| 10 | | Juin-Yeu Lu,
Shiu-Kai Chin:
Generating Designs Using an Algorithmic Register Transfer Language with Formal Semantics.
TPHOLs 1994: 316-331 |
| 1993 |
|---|
| 9 | | Juin-Yeu Lu,
Shiu-Kai Chin:
Linking HOL to a VLSI CAD System.
HUG 1993: 199-212 |
| 8 | | Stephen H. Brackin,
Shiu-Kai Chin:
Server-Process Restrictiveness in HOL.
HUG 1993: 450-463 |
| 1992 |
|---|
| 7 | EE | Shiu-Kai Chin:
Verified functions for generating signed-binary arithmetic hardware.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1529-1558 (1992) |
| 1991 |
|---|
| 6 | | Shiu-Kai Chin,
Graham M. Birtwistle:
Implementing and Verifying Finite-State Machines Using Types in Higher-Order Logic.
TPHOLs 1991: 121-129 |
| 5 | | Shiu-Kai Chin:
Verifying Arithmetic Hardware in Higher-Order Logic.
TPHOLs 1991: 22-31 |
| 1990 |
|---|
| 4 | EE | Shiu-Kai Chin,
Edward P. Stabler:
Synthesis of arithmetic hardware using hardware metafunctions.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 793-803 (1990) |
| 1989 |
|---|
| 3 | | Shiu-Kai Chin:
Combining Engineering Vigor with Mathematical Rigor.
Hardware Specification, Verification and Synthesis 1989: 152-176 |
| 2 | | Damir Jamsek,
Kevin J. Greene,
Shiu-Kai Chin,
Paul R. Humenn:
WINTER: WAMS in Tim Expression Reduction.
NACLP 1989: 1013-1029 |
| 1988 |
|---|
| 1 | EE | Shiu-Kai Chin,
Edward P. Stabler,
Kevin J. Greene:
Using higher order logic and functional languages to synthesize correct hardware.
ICCL 1988: 396-403 |
