2008 |
34 | EE | Ethan Hadar,
Gabriel M. Silberman:
Agile architecture methodology: long term strategy interleaved with short term tactics.
OOPSLA Companion 2008: 641-652 |
2003 |
33 | EE | Michael A. Bauer,
Gene F. Hoffnagle,
J. Howard Johnson,
Gabriel M. Silberman:
Introduction.
Information Systems Frontiers 5(2): 127-128 (2003) |
2002 |
32 | EE | Michael A. Bauer,
Gene F. Hoffnagle,
J. Howard Johnson,
Gabriel M. Silberman:
Introduction.
Information Systems Frontiers 4(4): 359-361 (2002) |
2001 |
31 | | Leon J. Osterweil,
Gabriel M. Silberman,
Kenny Wong:
New Software Engineering Faculty Symposium.
ICSE 2001: 813-813 |
1997 |
30 | | Stephen G. Perelgut,
Gabriel M. Silberman,
Kelly A. Lyons,
Karen Bennet:
Overview: The Centre for Advanced Studies.
IBM Systems Journal 36(4): 474-488 (1997) |
1996 |
29 | | Gabriel M. Silberman:
The Third International Conference on Parallel Computing Technologies (PaCT-95), Saint Petersburg, Russia.
SIGPLAN Notices 31(2): 8-9 (1996) |
1994 |
28 | | Michel Cosnard,
Guang R. Gao,
Gabriel M. Silberman:
Parallel Architectures and Compilation Techniques, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT'94, Montréal, Canada, 24-26 August, 1994
North-Holland 1994 |
27 | | Kemal Ebcioglu,
Randy D. Groves,
Ki-Chang Kim,
Gabriel M. Silberman,
Isaac Ziv:
VLIW Compilation Techniques in a Superscalar Environment.
PLDI 1994: 36-48 |
1993 |
26 | | Gabriel M. Silberman,
Kemal Ebcioglu:
An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures.
IEEE Computer 26(6): 39-56 (1993) |
25 | | Shlomit Weiss,
Ilan Y. Spillinger,
Gabriel M. Silberman:
Architectural Improvement for a Data-Driven VLSI Processing Array.
J. Parallel Distrib. Comput. 19(4): 308-322 (1993) |
1992 |
24 | EE | Gabriel M. Silberman,
Kemal Ebcioglu:
An architectural framework for migration from CISC to higher performance platforms.
ICS 1992: 198-215 |
1991 |
23 | | Gabriel M. Silberman,
Ilan Y. Spillinger:
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.
IEEE Trans. Computers 40(1): 66-79 (1991) |
22 | | Gabriel M. Silberman,
Ilan Y. Spillinger:
RIDDLE: A Foundation for Test Generation on a High-Level Design Description.
IEEE Trans. Computers 40(1): 80-87 (1991) |
1990 |
21 | EE | Gabriel M. Silberman,
Ilan Y. Spillinger:
Using functional fault simulation and the difference fault model to estimate implementation fault coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1335-1343 (1990) |
1989 |
20 | EE | Shlomit Weiss,
Ilan Y. Spillinger,
Gabriel M. Silberman:
Architectural Improvements for Data-Driven VLSI Processing Arrays.
FPCA 1989: 243-259 |
19 | | Raphael Renous,
Gabriel M. Silberman,
Ilan Y. Spillinger:
Whistle: A Workbench for Test Development of Library-Based Designs.
IEEE Computer 22(4): 27-41 (1989) |
1988 |
18 | | Gabriel M. Silberman,
Ilan Y. Spillinger:
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing.
ITC 1988: 764-772 |
17 | | Israel Koren,
Bilha Mendelson,
Irit Peled,
Gabriel M. Silberman:
A Data-Driven VLSI Array for Arbitrary Algorithms.
IEEE Computer 21(10): 30-43 (1988) |
16 | EE | Zeev Barzilai,
Daniel K. Beece,
Leendert M. Huisman,
Vijay S. Iyengar,
Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 838-849 (1988) |
15 | | Paul Erdös,
Israel Koren,
Shlomo Moran,
Gabriel M. Silberman,
Shmuel Zaks:
Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays.
Mathematical Systems Theory 21(2): 85-98 (1988) |
1987 |
14 | | Bilha Mendelson,
Gabriel M. Silberman:
An Improved Mapping of Data Flow Programs on a VLSI Array of Processors.
ICPP 1987: 871-873 |
13 | | Bilha Mendelson,
Gabriel M. Silberman:
Mapping Data Flow Programs on a VLSI Array of Processors.
ISCA 1987: 72-80 |
12 | | Michael Granski,
Israel Koren,
Gabriel M. Silberman:
The Effect of Operation Scheduling on the Performance of a Data Flow Computer.
IEEE Trans. Computers 36(9): 1019-1029 (1987) |
1986 |
11 | EE | Zeev Barzilai,
Daniel K. Beece,
Leendert M. Huisman,
Vijay S. Iyengar,
Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis.
DAC 1986: 164-170 |
10 | | Gabriel M. Silberman,
Ilan Y. Spillinger:
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage.
ITC 1986: 332-339 |
9 | | Zeev Barzilai,
J. Lawrence Carter,
Vijay S. Iyengar,
Indira Nair,
Barry K. Rosen,
Joe D. Rutledge,
Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models.
ITC 1986: 520-529 |
8 | EE | Ilan Y. Spillinger,
Gabriel M. Silberman:
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(3): 396-404 (1986) |
1985 |
7 | | Zeev Barzilai,
Vijay S. Iyengar,
Barry K. Rosen,
Gabriel M. Silberman:
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.
ITC 1985: 722-731 |
1984 |
6 | | Zeev Barzilai,
Daniel K. Beece,
Leendert M. Huisman,
Gabriel M. Silberman:
Using a Hardware Simulation Engine for Custom MOS Structured Designs.
IBM Journal of Research and Development 28(5): 564-571 (1984) |
5 | | Dan Gordon,
Israel Koren,
Gabriel M. Silberman:
Embedding Tree Stuctures in VLlSI Hexagonal Arrays.
IEEE Trans. Computers 33(1): 104-107 (1984) |
1983 |
4 | | Israel Koren,
Gabriel M. Silberman:
A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach.
ICPP 1983: 335-337 |
3 | | Gabriel M. Silberman:
Stack Processing Techniques in Delayed-Staging Storage Hierarchies.
Commun. ACM 26(11): 999-1007 (1983) |
2 | | Gabriel M. Silberman:
Delayed-Staging Hierarchy Optimization.
IEEE Trans. Computers 32(11): 1029-1037 (1983) |
1982 |
1 | | Gabriel M. Silberman:
Determining Fault Ratios in Multilevel Delayed-Staging Storage Hierarchies.
IEEE Trans. Computers 31(4): 305-310 (1982) |