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Ilan Y. Spillinger

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2000
15EEIlan Y. Spillinger, Chris J. Newburn: Guest Editors' Introduction. J. Instruction-Level Parallelism 2: (2000)
1996
14EEGuy Even, Ilan Y. Spillinger, Leon Stok: Retiming revisited and reversed. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 348-357 (1996)
1994
13 Gideon D. Intrater, Ilan Y. Spillinger: Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers. IEEE Trans. Computers 43(10): 1140-1150 (1994)
1993
12 Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman: Architectural Improvement for a Data-Driven VLSI Processing Array. J. Parallel Distrib. Comput. 19(4): 308-322 (1993)
1992
11 Gideon D. Intrater, Ilan Y. Spillinger: Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. ISCA 1992: 106-113
1991
10 Gabriel M. Silberman, Ilan Y. Spillinger: Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. IEEE Trans. Computers 40(1): 66-79 (1991)
9 Gabriel M. Silberman, Ilan Y. Spillinger: RIDDLE: A Foundation for Test Generation on a High-Level Design Description. IEEE Trans. Computers 40(1): 80-87 (1991)
1990
8EEGabriel M. Silberman, Ilan Y. Spillinger: Using functional fault simulation and the difference fault model to estimate implementation fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1335-1343 (1990)
1989
7EEShlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman: Architectural Improvements for Data-Driven VLSI Processing Arrays. FPCA 1989: 243-259
6 Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger: Whistle: A Workbench for Test Development of Library-Based Designs. IEEE Computer 22(4): 27-41 (1989)
1988
5 Gabriel M. Silberman, Ilan Y. Spillinger: G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. ITC 1988: 764-772
4 Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger: Delay Test Generation 1: Concepts and Coverage Metrics. ITC 1988: 857-866
3 Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger: Delay Test Generation 2: Algebra and Algorithms. ITC 1988: 867-876
1986
2 Gabriel M. Silberman, Ilan Y. Spillinger: The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. ITC 1986: 332-339
1EEIlan Y. Spillinger, Gabriel M. Silberman: Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. IEEE Trans. on CAD of Integrated Circuits and Systems 5(3): 396-404 (1986)

Coauthor Index

1Guy Even [14]
2Gideon D. Intrater [11] [13]
3Vijay S. Iyengar [3] [4]
4Chris J. Newburn [15]
5Raphael Renous [6]
6Barry K. Rosen [3] [4]
7Gabriel M. Silberman [1] [2] [5] [6] [7] [8] [9] [10] [12]
8Leon Stok [14]
9Shlomit Weiss [7] [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)