| 2008 |
|---|
| 11 | EE | Navin Srivastava,
Roberto Suaya,
Kaustav Banerjee:
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.
DATE 2008: 426-431 |
| 2007 |
|---|
| 10 | EE | Salvador Ortiz,
Roberto Suaya:
Efficient implementation of conduction modes for modelling skin effect.
ISVLSI 2007: 500-505 |
| 2006 |
|---|
| 9 | EE | Salvador Ortiz,
Roberto Suaya:
Fullwave volumetric Maxwell solver using conduction modes.
ICCAD 2006: 13-18 |
| 8 | EE | Rafael Escovar,
Salvador Ortiz,
Roberto Suaya:
Mutual inductance between intentional inductors: closed form expressions.
ISCAS 2006 |
| 2005 |
|---|
| 7 | EE | Chung-Kuan Cheng,
Steve Lin,
Andrew B. Kahng,
Keh-Jeng Chang,
Vijay Pitchumani,
Toshiyuki Shibuya,
Roberto Suaya,
Zhiping Yu,
Fook-Luen Heng,
Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
ASP-DAC 2005 |
| 6 | EE | Rafael Escovar,
Salvador Ortiz,
Roberto Suaya:
An improved long distance treatment for mutual inductance.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 783-793 (2005) |
| 2004 |
|---|
| 5 | EE | Rafael Escovar,
Salvador Ortiz,
Roberto Suaya:
Mutual inductance extraction and the dipole approximation.
ISPD 2004: 162-169 |
| 4 | EE | Rafael Escovar,
Roberto Suaya:
Optimal design of clock trees for multigigahertz applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 329-345 (2004) |
| 2002 |
|---|
| 3 | EE | Rafael Escovar,
Roberto Suaya:
Transmission line design of clock trees.
ICCAD 2002: 334-340 |
| 1991 |
|---|
| 2 | EE | Paul de Dood,
John Wawrzynek,
Erwin Liu,
Roberto Suaya:
A Two-Dimensional Topological Compactor With Octagonal Geometry.
DAC 1991: 727-731 |
| 1990 |
|---|
| 1 | EE | John Valainis,
Sinan Kaptanoglu,
Erwin Liu,
Roberto Suaya:
Two-dimensional IC layout compaction based on topological design rule checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 260-275 (1990) |
