| |
| 1996 | ||
|---|---|---|
| 10 | Silke Draber, Bernhard Eschermann: Dependability Evaluation of a Computing System for Traction Control of Electrical Locomotives. EDCC 1996: 129-140 | |
| 1994 | ||
| 9 | Bernhard Eschermann, Hubert D. Kirrmann: Fail-Safe On-Board Communication for Automatic Train Protection. GI Jahrestagung 1994: 356-363 | |
| 1993 | ||
| 8 | EE | Bernhard Eschermann: State Assignment for Hardwired VLSI Control Units. ACM Comput. Surv. 25(4): 415-436 (1993) |
| 7 | EE | Bernhard Eschermann: Enhancing on-line testability during synthesis. J. Electronic Testing 4(1): 105-116 (1993) |
| 1992 | ||
| 6 | Bernhard Eschermann: On Combining Off-Line BIST and On-Line Control Flow Checking. FTCS 1992: 298-305 | |
| 5 | EE | Bernhard Eschermann, Hans-Joachim Wunderlich: Optimized synthesis techniques for testable sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 301-312 (1992) |
| 4 | EE | Bernhard Eschermann: An implicitly testable boundary scan TAP controller. J. Electronic Testing 3(2): 159-169 (1992) |
| 1991 | ||
| 3 | EE | Bernhard Eschermann, Hans-Joachim Wunderlich: A Unified Approach for the Synthesis of Self-Testable Finite State Machines. DAC 1991: 372-377 |
| 2 | Bernhard Eschermann, Hans-Joachim Wunderlich: Emulation of Scan Paths in Sequential Circuit Synthesis. Fault-Tolerant Computing Systems 1991: 136-147 | |
| 1 | Juergen Froessl, Bernhard Eschermann: Module Generation for AND/XOR Fields (XPLAs). ICCD 1991: 26-29 | |
| 1 | Silke Draber | [10] |
| 2 | Juergen Froessl | [1] |
| 3 | Hubert D. Kirrmann | [9] |
| 4 | Hans-Joachim Wunderlich | [2] [3] [5] |