| 2006 |
|---|
| 12 | | Yung-Yuan Chen,
Kuen-Long Leu,
Li-Wen Lin:
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors.
CDES 2006: 196-202 |
| 11 | EE | Yung-Yuan Chen,
Kuen-Long Leu,
Chao-Sung Yeh:
Fault-Tolerant VLIW Processor Design and Error Coverage Analysis.
EUC 2006: 754-765 |
| 2005 |
|---|
| 10 | EE | Yung-Yuan Chen:
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring.
IEEE Trans. Computers 54(10): 1298-1313 (2005) |
| 2004 |
|---|
| 9 | EE | Yung-Yuan Chen,
Kun-Feng Chen:
Incorporating Signature-Monitoring Technique in VLIW Processors.
DFT 2004: 395-402 |
| 2003 |
|---|
| 8 | EE | Yung-Yuan Chen,
Shi-Jinn Horng,
Hung-Chuan Lai:
An Integrated Fault-Tolerant Design Framework for VLIW Processors.
DFT 2003: 555-562 |
| 1999 |
|---|
| 7 | EE | Yung-Yuan Chen:
Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring.
EDCC 1999: 437-454 |
| 1997 |
|---|
| 6 | | Yung-Yuan Chen,
Shambhu J. Upadhyaya,
Ching-Hwa Cheng:
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors.
IEEE Trans. Computers 46(12): 1363-1371 (1997) |
| 1995 |
|---|
| 5 | EE | Yung-Yuan Chen,
Ching-Hwa Cheng,
Jwu-E Chen:
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.
VLSI Design 1995: 349-354 |
| 1994 |
|---|
| 4 | | Yung-Yuan Chen,
Ching-Hwa Cheng,
Yung-Ci Chou:
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors.
EDCC 1994: 421-438 |
| 3 | | Yung-Yuan Chen,
Shambhu J. Upadhyaya:
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy.
IEEE Trans. Computers 43(6): 737-748 (1994) |
| 1993 |
|---|
| 2 | | Yung-Yuan Chen,
Shambhu J. Upadhyaya:
Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy.
IEEE Trans. Computers 42(6): 713-723 (1993) |
| 1 | | Yung-Yuan Chen,
Shambhu J. Upadhyaya:
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy.
IEEE Trans. Computers 42(9): 1136-1141 (1993) |
