| 1999 |
|---|
| 11 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.
VLSI Signal Processing 21(1): 37-60 (1999) |
| 1998 |
|---|
| 10 | EE | S. K. Misra,
R. K. Kolagotla,
Hosahalli R. Srinivas,
J. C. Mo,
M. S. Diamondstein:
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.
VLSI Design 1998: 326-329 |
| 1997 |
|---|
| 9 | | Hosahalli R. Srinivas,
Keshab K. Parhi,
Luis A. Montalvo:
Radix 2 Division with Over-Redundant Quotient Selection.
IEEE Trans. Computers 46(1): 85-92 (1997) |
| 1995 |
|---|
| 8 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
A floating point radix 2 shared division/square root chip.
ICCD 1995: 472-478 |
| 7 | EE | W. Amendola Jr.,
Hosahalli R. Srinivas,
Keshab K. Parhi:
A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.
VLSI Design 1995: 398-402 |
| 6 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Fast Radix-4 Division Algorithm and Its Architecture.
IEEE Trans. Computers 44(6): 826-831 (1995) |
| 1994 |
|---|
| 5 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Fast Radix-4 Division Algorithm.
ISCAS 1994: 311-314 |
| 4 | EE | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-testable carry-free divider.
IEEE Trans. VLSI Syst. 2(4): 472-488 (1994) |
| 1993 |
|---|
| 3 | | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-Testable Carry-Free Divider.
ICCD 1993: 206-213 |
| 1992 |
|---|
| 2 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
High-speed VLSI arithmetic processor architectures using hybrid number representation.
VLSI Signal Processing 4(2-3): 177-198 (1992) |
| 1991 |
|---|
| 1 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation.
ICCD 1991: 564-571 |
