| 2007 |
|---|
| 8 | EE | David Guerrero,
Alejandro Millán,
Jorge Juan-Chico,
Manuel J. Bellido,
Paulino Ruiz-de-Clavijo,
Enrique Ostúa,
Julian Viejo:
Static Power Consumption in CMOS Gates Using Independent Bodies.
PATMOS 2007: 404-412 |
| 7 | EE | Julian Viejo,
Alejandro Millán,
Manuel J. Bellido,
Jorge Juan,
Paulino Ruiz-de-Clavijo,
David Guerrero,
Enrique Ostúa,
A. Munoz:
Design of a FFT/IFFT module as an IP core suitable for embedded systems.
SIES 2007: 337-340 |
| 6 | EE | David Guerrero,
Alejandro Millán,
Jorge Juan-Chico,
Manuel Jesús Bellido Díaz,
Paulino Ruiz-de-Clavijo,
Enrique Ostúa,
Julian Viejo:
Improving the Performance of Static CMOS Gates by Using Independent Bodies.
J. Low Power Electronics 3(1): 70-77 (2007) |
| 2006 |
|---|
| 5 | EE | Paulino Ruiz-de-Clavijo,
Jorge Juan-Chico,
Manuel Jesús Bellido Díaz,
Alejandro Millán,
David Guerrero,
Enrique Ostúa,
Julian Viejo:
Accurate Logic-Level Current Estimation for Digital CMOS Circuits.
J. Low Power Electronics 2(1): 87-94 (2006) |
| 2005 |
|---|
| 4 | EE | Alejandro Millán Calderón,
Manuel Jesús Bellido Díaz,
Jorge Juan-Chico,
Paulino Ruiz-de-Clavijo,
David Guerrero Martos,
Enrique Ostúa,
Julian Viejo:
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.
PATMOS 2005: 337-347 |
| 3 | EE | Paulino Ruiz-de-Clavijo,
Jorge Juan-Chico,
Manuel Jesús Bellido Díaz,
Alejandro Millán Calderón,
David Guerrero Martos,
Enrique Ostúa,
Julian Viejo:
Logic-Level Fast Current Simulation for Digital CMOS Circuits.
PATMOS 2005: 425-435 |
| 2004 |
|---|
| 2 | EE | Alejandro Millán,
Jorge Juan-Chico,
Manuel J. Bellido,
Paulino Ruiz-de-Clavijo,
David Guerrero,
Enrique Ostúa:
Signal Sampling Based Transition Modeling for Digital Gates Characterization.
PATMOS 2004: 829-837 |
| 2003 |
|---|
| 1 | EE | Alejandro Millán,
Manuel J. Bellido,
Jorge Juan-Chico,
David Guerrero,
Paulino Ruiz-de-Clavijo,
Enrique Ostúa:
Internode: Internal Node Logic Computational Model.
Annual Simulation Symposium 2003: 241-248 |
