Alejandro Millán

Alejandro Millán Calderón

2008
12	EE	Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398
2007
11	EE	David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412
10	EE	Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa, A. Munoz: Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340
9	EE	David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electronics 3(1): 70-77 (2007)
2006
8	EE	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, Julian Viejo: Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electronics 2(1): 87-94 (2006)
2005
7	EE	Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347
6	EE	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435
2004
5	EE	Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa: Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837
2003
4	EE	Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa: Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248
3	EE	David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán: Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510
2002
2	EE	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero: Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408
1	EE	Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero: Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486

Coauthor Index

1	Manuel Jesús Bellido Díaz (Manuel J. Bellido)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
2	David Guerrero	[1] [2] [3] [4] [5] [8] [9] [10] [11] [12]
3	José Luís Almada Güntzel	[3]
4	Jorge Juan	[10] [12]
5	Jorge Juan-Chico	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11]
6	David Guerrero Martos	[6] [7]
7	A. Munoz	[10]
8	Enrique Ostúa	[4] [5] [6] [7] [8] [9] [10] [11]
9	Paulino Ruiz-de-Clavijo	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
10	Julian Viejo	[6] [7] [8] [9] [10] [11] [12]
11	Gustavo Wilke	[3]