2008 |
18 | EE | José L. Risco-Martín,
José Ignacio Hidalgo,
Juan Lanchares,
Oscar Garnica:
Solving discrete deceptive problems with EMMRS.
GECCO 2008: 1139-1140 |
17 | EE | José Manuel Colmenar,
Noelia Morón,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo:
Modelling Asynchronous Systems using Probability Distribution Functions.
PDP 2008: 3-11 |
2007 |
16 | EE | Sonia López,
Steve Dropsho,
David H. Albonesi,
Oscar Garnica,
Juan Lanchares:
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.
HiPEAC 2007: 136-150 |
15 | EE | Sonia López,
Steven G. Dropsho,
David H. Albonesi,
Oscar Garnica,
Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.
PACT 2007: 416 |
2006 |
14 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
DSD 2006: 423-432 |
13 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
A Power-Aware Technique for Functional Units in High-Performance Processors.
DSD 2006: 456-459 |
12 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.
Euro-Par 2006: 495-505 |
11 | EE | Guadalupe Miñana,
José Ignacio Hidalgo,
Oscar Garnica,
Juan Lanchares,
José Manuel Colmenar,
Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.
PATMOS 2006: 514-523 |
2005 |
10 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.
PATMOS 2005: 40-48 |
2004 |
9 | EE | Sonia López,
Oscar Garnica,
José Manuel Colmenar:
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.
PATMOS 2004: 623-632 |
8 | EE | José Manuel Colmenar,
Oscar Garnica,
Sonia López,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
PDP 2004: 112-119 |
2003 |
7 | EE | José Ignacio Hidalgo,
Francisco Fernández de Vega,
Juan Lanchares,
Juan Manuel Sánchez-Pérez,
Román Hermida,
Marco Tomassini,
Ranieri Baraglia,
Raffaele Perego,
Oscar Garnica:
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation.
GECCO 2003: 2109-2120 |
6 | EE | Sonia López,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
PATMOS 2003: 151-160 |
5 | EE | José Ignacio Hidalgo,
Manuel Prieto,
Juan Lanchares,
Ranieri Baraglia,
Francisco Tirado,
Oscar Garnica:
Hybrid Parallelization of a Compact Genetic Algorithm.
PDP 2003: 449-455 |
2002 |
4 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
A New Methodology to Design Low-Power Asynchronous Circuits.
PATMOS 2002: 108-117 |
3 | | Oscar Garnica,
Juan Lanchares,
Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.
Fundam. Inform. 50(2): 155-174 (2002) |
2001 |
2 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.
ACSD 2001: 167-178 |
1 | EE | Oscar Garnica,
Juan Lanchares,
Román Hermida:
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.
DATE 2001: 810 |