2008 |
24 | EE | Antoine Courtay,
Johann Laurent,
Olivier Sentieys,
Nathalie Julien:
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
PATMOS 2008: 359-368 |
23 | EE | Gwenolé Corre,
Eric Senn,
Nathalie Julien,
Eric Martin:
Estimation et optimisation de la consommation des mémoires.
Technique et Science Informatiques 27(1-2): 235-254 (2008) |
2007 |
22 | EE | Johann Laurent,
Eric Senn,
Nathalie Julien:
Méthodes et outils d'estimation de la consommation de code embarqué sur processeur.
Technique et Science Informatiques 26(5): 509-534 (2007) |
2006 |
21 | EE | David Elléouet,
Nathalie Julien,
Dominique Houzet:
A high level SoC power estimation based on IP modeling.
IPDPS 2006 |
20 | EE | David Elléouet,
Yannig Savary,
Nathalie Julien:
An FPGA Power Aware Design Flow.
PATMOS 2006: 415-424 |
19 | | Eric Senn,
Nathalie Julien,
David Elléouet,
Yannig Savary,
Nabil Abdelli:
Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design.
ReCoSoC 2006: 83-90 |
18 | EE | Gwenolé Corre,
Nathalie Julien,
Eric Senn,
Eric Martin:
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power
CoRR abs/cs/0605142: (2006) |
17 | EE | Gwenolé Corre,
Nathalie Julien,
Eric Senn,
Eric Martin:
A Memory Aware High Level Synthesis Too
CoRR abs/cs/0605144: (2006) |
16 | EE | Gwenolé Corre,
Eric Senn,
Nathalie Julien,
Eric Martin:
Memory Aware High-Level Synthesis for Embedded Systems
CoRR abs/cs/0605145: (2006) |
2005 |
15 | | Nathalie Julien,
Johann Laurent,
Eric Senn,
David Elléouet,
Yannig Savary,
Nabil Abdelli,
J. Ktari:
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling.
ReCoSoC 2005: 137-142 |
2004 |
14 | EE | Gwenolé Corre,
Eric Senn,
Nathalie Julien,
Eric Martin:
A memory aware behavioral synthesis tool for real-time VLSI circuits.
ACM Great Lakes Symposium on VLSI 2004: 82-85 |
13 | EE | Gwenolé Corre,
Eric Senn,
Pierre Bomel,
Nathalie Julien,
Eric Martin:
Memory accesses management during high level synthesis.
CODES+ISSS 2004: 42-47 |
12 | EE | Johann Laurent,
Nathalie Julien,
Eric Senn,
Eric Martin:
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors.
DATE 2004: 666-667 |
11 | EE | David Elléouet,
Nathalie Julien,
Dominique Houzet,
J.-G. Cousin,
Eric Martin:
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.
DSD 2004: 394-401 |
10 | EE | Gwenolé Corre,
Eric Senn,
Nathalie Julien,
Eric Martin:
Memory Aware HLS and the Implementation of Ageing Vectors.
DSD 2004: 88-95 |
9 | EE | Florian Marteil,
Nathalie Julien,
Eric Senn,
Eric Martin:
A Complete Methodology for Memory Optimization in DSP Applications.
DSD 2004: 98-103 |
8 | EE | Gwenolé Corre,
Eric Senn,
Nathalie Julien,
Eric Martin:
A Memory Aware High Level Synthesis Tool .
ISVLSI 2004: 279-280 |
7 | EE | Eric Senn,
Johann Laurent,
Nathalie Julien,
Eric Martin:
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.
PATMOS 2004: 342-351 |
2003 |
6 | EE | Nathalie Julien,
Johann Laurent,
Eric Senn,
Eric Martin:
Power Consumption Modeling and Characterization of the TI C6201.
IEEE Micro 23(5): 40-49 (2003) |
5 | EE | Nathalie Julien,
S. Gailhard,
Eric Martin:
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT.
VLSI Signal Processing 35(2): 195-211 (2003) |
2002 |
4 | EE | Nathalie Julien,
Johann Laurent,
Eric Senn,
Eric Martin:
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor.
ISHPC 2002: 354-360 |
3 | EE | Eric Senn,
Nathalie Julien,
Johann Laurent,
Eric Martin:
Power Consumption Estimation of a C Program for Data-Intensive Applications.
PATMOS 2002: 332-341 |
1999 |
2 | EE | S. Gailhard,
Nathalie Julien,
Adel Baganne,
Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
Great Lakes Symposium on VLSI 1999: 334-335 |
1998 |
1 | EE | S. Gailhard,
Nathalie Julien,
Jean-Philippe Diguet,
Eric Martin:
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs.
Great Lakes Symposium on VLSI 1998: 426- |