| 2005 |
|---|
| 9 | EE | Mario Polaschegg,
Christian Steger,
Damian Dalton,
Abhay Vadher:
Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling.
ICPP Workshops 2005: 251-257 |
| 8 | EE | Alexander Maili,
Christian Steger,
Reinhold Weiss,
Rob Quigley,
Damian Dalton:
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.
ISVLSI 2005: 290-291 |
| 2004 |
|---|
| 7 | EE | Mario Polaschegg,
Christian Steger,
Damian Dalton,
Abhay Vadher:
A Generic Simulation Framework for Multiprocessor Architectures.
FDL 2004: 345-355 |
| 6 | EE | Alexander Maili,
Damian Dalton,
Christian Steger:
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.
PATMOS 2004: 799-808 |
| 2003 |
|---|
| 5 | EE | Damian Dalton,
Vivian Bessler,
Jeffrey Griffiths,
Andrew McCarthy,
Abhay Vadher,
Rory O'Kane,
Rob Quigley,
Declan O'Connor:
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator.
FPL 2003: 1162-1165 |
| 1999 |
|---|
| 4 | | Damian Dalton:
Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture.
HiPC 1999: 364-370 |
| 3 | EE | Damian Dalton:
Analysis of an Associative Array Parallel Logic Simulator.
ICPP Workshops 1999: 308-312 |
| 2 | | Damian Dalton:
A New Timing Mechanism Architecture for Discrete Logic Event Simulation.
PDPTA 1999: 1236-1242 |
| 1 | EE | Damian Dalton:
The Speedup Performance of an Associative Memory Based Logic Simulator.
PaCT 1999: 207-216 |
