| 2006 |
|---|
| 4 | EE | Alexandre Verle,
A. Landrault,
Philippe Maurine,
Nadine Azémard:
Circuit sizing method under delay constraint.
ISCAS 2006 |
| 2005 |
|---|
| 3 | EE | Alexandre Verle,
A. Landrault,
Philippe Maurine,
Nadine Azémard:
Speed Indicators for Circuit Optimization.
PATMOS 2005: 618-628 |
| 2004 |
|---|
| 2 | EE | A. Landrault,
Nadine Azémard,
Philippe Maurine,
Michel Robert,
Daniel Auvergne:
Design Optimization with Automated Cell Generation.
PATMOS 2004: 722-731 |
| 2002 |
|---|
| 1 | EE | A. Landrault,
L. Pellier,
A. Richard,
C. Jay,
Michel Robert,
Daniel Auvergne:
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.
PATMOS 2002: 156-166 |
