| 2006 |
|---|
| 9 | EE | Daniel Lima Ferrão,
Ricardo Reis,
José Luís Almada Güntzel:
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.
PATMOS 2006: 301-310 |
| 2004 |
|---|
| 8 | EE | Ricardo Reis,
Fernanda Lima Kastensmidt,
José Luís Almada Güntzel:
Physical design methodologies for performance predictability and manufacturability.
Conf. Computing Frontiers 2004: 390-397 |
| 7 | EE | Fabricio B. Bastian,
Cristiano Lazzari,
José Luís Almada Güntzel,
Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.
PATMOS 2004: 732-741 |
| 2003 |
|---|
| 6 | EE | David Guerrero,
Gustavo Wilke,
José Luís Almada Güntzel,
Manuel J. Bellido,
Jorge Juan-Chico,
Paulino Ruiz-de-Clavijo,
Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
PATMOS 2003: 501-510 |
| 5 | EE | Daniel Lima Ferrão,
Gustavo Wilke,
Ricardo Augusto da Luz Reis,
José Luís Almada Güntzel:
Improving Critical Path Identification in Functional Timing Analysis.
SBCCI 2003: 297-302 |
| 4 | EE | Cristiano Santos,
Gustavo Wilke,
Cristiano Lazzari,
Ricardo Reis,
José Luís Almada Güntzel:
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.
SBCCI 2003: 303- |
| 3 | | Cristiano Lazzari,
Cristiano Viana Domingues,
José Luís Almada Güntzel,
Ricardo Augusto da Luz Reis:
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies.
VLSI-SOC 2003: 193-197 |
| 2001 |
|---|
| 2 | | José Luís Almada Güntzel,
Ricardo Augusto da Luz Reis:
Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas.
RITA 8(1): 111-142 (2001) |
| 1999 |
|---|
| 1 | | Fernanda Lima,
Marcelo O. Johann,
José Luís Almada Güntzel,
Eduardo D'Avila,
Luigi Carro,
Ricardo Augusto da Luz Reis:
Designing a Mask Programmable Matrix for Sequential Circuits.
VLSI 1999: 439-446 |
