| 2006 |
|---|
| 7 | EE | Matthias Müller,
Sven Simon,
Holger Gryska,
Andreas Wortmann,
Steffen Buch:
Low power synthesizable register files for processor and IP cores.
Integration 39(2): 131-155 (2006) |
| 2004 |
|---|
| 6 | EE | Andreas Wortmann,
Sven Simon,
Matthias Müller:
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.
DATE 2004: 46-51 |
| 5 | | Sven Simon,
Matthias Müller,
Holger Gryska,
Andreas Wortmann,
Steffen Buch:
An instruction set for the efficient implementation of the CORDIC algorithm.
ISCAS (2) 2004: 357-360 |
| 4 | | Matthias Müller,
Andreas Wortmann,
Sven Simon,
Michael Kugel,
Tim Schoenauer:
The impact of clock gating schemes on the power dissipation of synthesizable register files.
ISCAS (2) 2004: 609-612 |
| 3 | EE | Matthias Müller,
Andreas Wortmann,
Dominik Mader,
Sven Simon:
Register Isolation for Synthesizable Register Files.
PATMOS 2004: 228-237 |
| 2003 |
|---|
| 2 | EE | Marek Wróblewski,
Matthias Müller,
Andreas Wortmann,
Sven Simon,
Wilhelm Pieper,
Josef A. Nossek:
A power efficient register file architecture using master latch sharing.
ISCAS (5) 2003: 393-396 |
| 2002 |
|---|
| 1 | EE | Matthias Müller,
Andreas Wortmann,
Sven Simon,
S. Wolter,
Steffen Buch,
Marek Wróblewski,
Josef A. Nossek:
Low power register file architecture for application specific DSPs.
ISCAS (4) 2002: 89-92 |
