| 2004 |
|---|
| 6 | EE | Peter Celinski,
Said F. Al-Sarawi,
Derek Abbott,
Sorin Cotofana,
Stamatis Vassiliadis:
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.
ISVLSI 2004: 127-134 |
| 5 | EE | Troy D. Townsend,
Peter Celinski,
Said F. Al-Sarawi,
Michael J. Liebelt:
Hybrid Parallel Counters - Domino and Threshold Logic.
ISVLSI 2004: 275-276 |
| 4 | EE | Peter Celinski,
Derek Abbott,
Sorin Cotofana:
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.
PATMOS 2004: 899-906 |
| 2003 |
|---|
| 3 | EE | Peter Celinski,
Derek Abbott,
Sorin Dan Cotofana:
Area efficient, high speed parallel counter circuits using charge recycling threshold logic.
ISCAS (5) 2003: 233-236 |
| 2 | EE | Peter Celinski,
Sorin Cotofana,
Derek Abbott:
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.
IWANN (2) 2003: 73-80 |
| 2002 |
|---|
| 1 | EE | Peter Celinski,
Said F. Al-Sarawi,
Derek Abbott,
José Francisco López:
Low depth carry lookahead addition using charge recycling threshold logic.
ISCAS (1) 2002: 469-472 |
