| 2007 |
|---|
| 8 | EE | Alexandre Verle,
Xavier Michel,
Nadine Azémard,
Philippe Maurine,
Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol
CoRR abs/0710.4760: (2007) |
| 2006 |
|---|
| 7 | EE | Alexandre Verle,
A. Landrault,
Philippe Maurine,
Nadine Azémard:
Circuit sizing method under delay constraint.
ISCAS 2006 |
| 2005 |
|---|
| 6 | EE | Alexandre Verle,
Xavier Michel,
Nadine Azémard,
Philippe Maurine,
Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol.
DATE 2005: 640-645 |
| 5 | EE | Alexandre Verle,
A. Landrault,
Philippe Maurine,
Nadine Azémard:
Speed Indicators for Circuit Optimization.
PATMOS 2005: 618-628 |
| 2004 |
|---|
| 4 | | Alexandre Verle,
Xavier Michel,
Philippe Maurine,
Nadine Azémard,
Daniel Auvergne:
Delay bound based CMOS gate sizing technique.
ISCAS (5) 2004: 189-192 |
| 3 | EE | Xavier Michel,
Alexandre Verle,
Philippe Maurine,
Nadine Azémard,
Daniel Auvergne:
Performance Metric Based Optimization Protocol.
PATMOS 2004: 100-109 |
| 2003 |
|---|
| 2 | EE | Xavier Michel,
Alexandre Verle,
Nadine Azémard,
Philippe Maurine,
Daniel Auvergne:
Metric Definition for Circuit Speed Optimization.
PATMOS 2003: 451-460 |
| 1 | EE | Alexandre Verle,
Xavier Michel,
Philippe Maurine,
Nadine Azémard,
Daniel Auvergne:
CMOS Gate Sizing under Delay Constraint.
PATMOS 2003: 60-69 |
