| 2008 |
|---|
| 7 | EE | Yici Cai,
Jin Shi,
Zhu Pan,
Xianlong Hong,
Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach.
Integration 41(1): 153-160 (2008) |
| 2006 |
|---|
| 6 | EE | Zuying Luo,
Yici Cai,
Sheldon X.-D. Tan,
Xianlong Hong,
Xiaoyi Wang,
Zhu Pan,
Jingjing Fu:
Time-domain analysis methodology for large-scale RLC circuits and its applications.
Science in China Series F: Information Sciences 49(5): 665-680 (2006) |
| 2005 |
|---|
| 5 | EE | Yici Cai,
Zhu Pan,
Sheldon X.-D. Tan,
Xianlong Hong,
Wenting Hou,
Lifeng Wu:
Relaxed hierarchical power/ground grid analysis.
ASP-DAC 2005: 1090-1093 |
| 4 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
VLSI on-chip power/ground network optimization considering decap leakage currents.
ASP-DAC 2005: 735-738 |
| 2004 |
|---|
| 3 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
ASP-DAC 2004: 505-510 |
| 2 | EE | Zhu Pan,
Yici Cai,
Sheldon X.-D. Tan,
Zuying Luo,
Xianlong Hong:
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
ISQED 2004: 63-68 |
| 1 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
PATMOS 2004: 433-441 |
