David Guerrero

2008
13	EE	Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398
2007
12	EE	David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412
11	EE	Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa, A. Munoz: Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340
10	EE	David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electronics 3(1): 70-77 (2007)
9	EE	Maria Pinto, Dora Sales, Anne-Vinciane Doucet, Andrés Fernández-Ramos, David Guerrero: Metric analysis of the information visibility and diffusion about the European Higher Education Area on Spanish University websites. Scientometrics 72(2): 345-370 (2007)
2006
8	EE	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, Julian Viejo: Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electronics 2(1): 87-94 (2006)
2004
7	EE	Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa: Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837
2003
6	EE	Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa: Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248
5	EE	David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán: Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510
2002
4	EE	Miguel Caballer, David Guerrero, Vicente Hernández, José E. Román, Mariano Alcañiz Raya, José Antonio Gil, J. M. Rubio: High Performance Virtual Reality Distributed Electronic Commerce: Application for the Furniture and Ceramics Industries. IV 2002: 516-521
3	EE	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero: Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408
2	EE	Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero: Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486
1	EE	Miguel Caballer, David Guerrero, Vicente Hernández, José E. Román: A Parallel Rendering Algorithm Based on Hierarchical Radiosity. VECPAR 2002: 523-536

Coauthor Index

1	Miguel Caballer	[1] [4]
2	Manuel Jesús Bellido Díaz (Manuel J. Bellido)	[2] [3] [5] [6] [7] [8] [10] [11] [12] [13]
3	Anne-Vinciane Doucet	[9]
4	Andrés Fernández-Ramos	[9]
5	José Antonio Gil	[4]
6	José Luís Almada Güntzel	[5]
7	Vicente Hernández	[1] [4]
8	Jorge Juan	[11] [13]
9	Jorge Juan-Chico	[2] [3] [5] [6] [7] [8] [10] [12]
10	Alejandro Millán (Alejandro Millán Calderón)	[2] [3] [5] [6] [7] [8] [10] [11] [12] [13]
11	A. Munoz	[11]
12	Enrique Ostúa	[6] [7] [8] [10] [11] [12]
13	Maria Pinto	[9]
14	Mariano Alcañiz Raya	[4]
15	José E. Román	[1] [4]
16	J. M. Rubio	[4]
17	Paulino Ruiz-de-Clavijo	[2] [3] [5] [6] [7] [8] [10] [11] [12] [13]
18	Dora Sales	[9]
19	Julian Viejo	[8] [10] [11] [12] [13]
20	Gustavo Wilke	[5]

Colors in the list of coauthors