2007 |
12 | EE | Delong Shang,
Chi-Hoon Shin,
Ping Wang,
Fei Xia,
Albert Koelmans,
Myeong-Hoon Oh,
Seongwoon Kim,
Alexandre Yakovlev:
Asynchronous Functional Coupling for Low Power Sensor Network Processors.
PATMOS 2007: 53-63 |
11 | EE | Delong Shang,
Alexandre Yakovlev,
Albert Koelmans,
Danil Sokolov,
Alexandre V. Bystrov:
Registers for Phase Difference Based Logic.
IEEE Trans. VLSI Syst. 15(6): 720-724 (2007) |
2004 |
10 | EE | Frank P. Burns,
Delong Shang,
Albert Koelmans,
Alexandre Yakovlev:
An Asynchronous Synthesis Toolset Using Verilog.
DATE 2004: 724-725 |
9 | EE | Delong Shang,
Frank P. Burns,
Alexandre V. Bystrov,
Albert Koelmans,
Danil Sokolov,
Alexandre Yakovlev:
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.
PATMOS 2004: 471-480 |
2001 |
8 | | Alan Burns,
Andy J. Wellings,
Frank P. Burns,
Albert Koelmans,
Maciej Koutny,
Alexander B. Romanovsky,
Alexandre Yakovlev:
Modelling and verification of an atomic action protocol implemented in Ada.
Comput. Syst. Sci. Eng. 16(3): 173-182 (2001) |
2000 |
7 | EE | Fei Xia,
Alexandre Yakovlev,
Delong Shang,
Alexandre V. Bystrov,
Albert Koelmans,
D. J. Kinniment:
Asynchronous Communication Mechanisms Using Self-Timed Circuits.
ASYNC 2000: 150- |
6 | | Frank P. Burns,
Albert Koelmans,
Alexandre Yakovlev:
WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets.
Real-Time Systems 18(2/3): 275-288 (2000) |
1998 |
5 | EE | Frank P. Burns,
Albert Koelmans,
Alexandre Yakovlev:
Analysing Superscalar Processor Architectures with Coloured Petri Nets.
STTT 2(2): 182-191 (1998) |
1996 |
4 | EE | J. N. Coleman,
Frank P. Burns,
D. J. Kinniment,
T. J. Butler,
Albert Koelmans:
A self-taught computer engineering course.
ACSE 1996: 7-12 |
3 | EE | Alexandre Yakovlev,
Albert Koelmans,
Alexei L. Semenov,
D. J. Kinniment:
Modelling, analysis and synthesis of asynchronous control circuits using Petri nets.
Integration 21(3): 143-170 (1996) |
1995 |
2 | EE | Alexandre Yakovlev,
Albert Koelmans,
Luciano Lavagno:
High-Level Modeling and Design of Asynchronous Interface Logic.
IEEE Design & Test of Computers 12(1): 32-40 (1995) |
1992 |
1 | | D. J. Kinniment,
Albert Koelmans:
Modelling and Verification of Timing Conditions with the Boyer Moore Prover.
TPCD 1992: 111-127 |