| 2008 |
|---|
| 7 | EE | Masaaki Iijima,
Kayoko Seto,
Masahiro Numa,
Akira Tada,
Takashi Ipposhi:
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation.
JCP 3(5): 34-40 (2008) |
| 2007 |
|---|
| 6 | EE | Masaaki Iijima,
Masayuki Kitamura,
Masahiro Numa,
Akira Tada,
Takashi Ipposhi:
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.
VLSI Design 2007: 609-614 |
| 5 | EE | Masaaki Iijima,
Kayoko Seto,
Masahiro Numa,
Akira Tada,
Takashi Ipposhi:
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM.
IEICE Transactions 90-A(12): 2691-2694 (2007) |
| 4 | EE | Masaaki Iijima,
Masayuki Kitamura,
Masahiro Numa,
Akira Tada,
Takashi Ipposhi,
Shigeto Maegawa:
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation.
IEICE Transactions 90-C(4): 666-674 (2007) |
| 2006 |
|---|
| 3 | EE | Masayuki Kitamura,
Masaaki Iijima,
Kenji Hamada,
Masahiro Numa,
Hiromi Notani,
Akira Tada,
Shigeto Maegawa:
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.
PATMOS 2006: 393-402 |
| 2004 |
|---|
| 2 | | Kazuki Fukuoka,
Masaaki Iijima,
Kenji Hamada,
Masahiro Numa,
Akira Tada:
Leakage power reduction for clock gating scheme on PD-SOI.
ISCAS (2) 2004: 613-616 |
| 1 | EE | Kazuki Fukuoka,
Masaaki Iijima,
Kenji Hamada,
Masahiro Numa,
Akira Tada:
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.
PATMOS 2004: 423-432 |
