| 2007 |
|---|
| 9 | EE | Kiyoo Itoh,
Masanao Yamaoka,
Takayuki Kawahara:
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.
ACM Great Lakes Symposium on VLSI 2007: 529-533 |
| 8 | EE | Riichiro Takemura,
Kiyoo Itoh,
Tomonori Sekiguchi,
Satoru Akiyama,
Satoru Hanzawa,
Kazuhiko Kajigaya,
Takayuki Kawahara:
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation.
IEICE Transactions 90-C(4): 758-764 (2007) |
| 2006 |
|---|
| 7 | EE | Kiyoo Itoh,
Masashi Horiguchi,
Takayuki Kawahara:
Ultra-low voltage nano-scale embedded RAMs.
ISCAS 2006 |
| 6 | EE | Riichiro Takemura,
Kiyoo Itoh,
Tomonori Sekiguchi:
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers.
ISLPED 2006: 123-126 |
| 2004 |
|---|
| 5 | EE | Kiyoo Itoh,
Kenichi Osada,
Takayuki Kawahara:
Low-Voltage Embedded RAMs - Current Status and Future Trends.
PATMOS 2004: 3-15 |
| 2003 |
|---|
| 4 | EE | Yoshinobu Nakagome,
Masashi Horiguchi,
Takayuki Kawahara,
Kiyoo Itoh:
Review and future prospects of low-voltage RAM circuits.
IBM Journal of Research and Development 47(5-6): 525-552 (2003) |
| 2002 |
|---|
| 3 | EE | Kiyoo Itoh:
Low-voltage memories for power-aware systems.
ISLPED 2002: 1-6 |
| 2 | EE | Kiyoo Itoh:
Trends in Ultralow-Voltage RAM Technology.
PATMOS 2002: 300-313 |
| 2001 |
|---|
| 1 | | Kiyoo Itoh,
Hiroyuki Mizuno:
Low-Voltage Embedded-RAM Technology: Present and Future.
VLSI-SOC 2001: 277-288 |
