Daniele D. Caviglia

2005
14	EE	Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia: Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. SBCCI 2005: 149-153
13	EE	Giovanna Morgavi, Mauro Morando, Grazia Biorci, Daniele D. Caviglia: Growing up: emerging complexity in living being. Cybernetics and Systems 36(4): 379-395 (2005)
2000
12	EE	Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia: Evaluation of Gradient Descent Learning Algorithms with an Adaptive Local Rate Technique for Hierarchical Feed Forward Architectures. IJCNN (2) 2000: 185-190
11	EE	Francesco Diotalevi, Maurizio Valle, Gian Marco Bo, Daniele D. Caviglia: A VLSI Architecture for Weight Perturbation on Chip Learning Implementation. IJCNN (4) 2000: 219-226
10	EE	Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle: An On-Chip Learning Neural Network. IJCNN (4) 2000: 66-74
1999
9		Francesco Diotalevi, Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle: Evaluation and Validation of Local and Adaptive Weight Perturbation Learning Algorithms for Optical Characters Recognition Applications. IIA/SOCO 1999
8		Daniela Baratta, Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia: Gradient Descent Learning Algorithm for Hierarchical Neural Networks: A Case Study in Industrial Quality. IWANN (2) 1999: 578-587
1997
7		Daniela Baratta, Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle, Giovanni Canepa, Riccardo Parenti, Carla Penno: A Hardware Implementation of Hierarchical Neural Networks for Real-Time Quality Contol Systems in Industrial Applications. ICANN 1997: 1229-1234
1996
6	EE	Maurizio Valle, Luigi Raffo, Daniele D. Caviglia, Giacomo M. Bisio: A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant. Real-Time Imaging 2(6): 361-371 (1996)
1994
5	EE	Maurizio Valle, Daniele D. Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo: A VHDL-based design methodology: the design experience of a high performance ASIC chip. EURO-DAC 1994: 664-669
1992
4		Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio: Optimization strategies in symbolic compaction. Synthesis for Control Dominated Circuits 1992: 311-322
1991
3		Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio: A VLSI Module for Analog Adaptive Neural Architectures. VLSI 1991: 177-186
2	EE	Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio: Symbolic generation of constrained random logic cells. IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 220-231 (1991)
1990
1	EE	Daniele D. Caviglia, Giacomo M. Bisio, Francesco Curatelli, L. Giovannacci, Luigi Raffo: Pre-placement of VLSI blocks through learning neural networks. EURO-DAC 1990: 650-654

Coauthor Index

1	Daniela Baratta	[7] [8]
2	Grazia Biorci	[13]
3	Giacomo M. Bisio	[1] [2] [3] [4] [6]
4	Gian Marco Bo	[7] [9] [10] [11]
5	Luciano Briozzo	[5]
6	Giovanni Canepa	[7]
7	Marco Chirico	[4]
8	Marco Cornero	[5]
9	Raffaele Costa	[2]
10	Francesco Curatelli	[1] [2] [4]
11	Francesco Diotalevi	[8] [9] [11] [12]
12	Sergio Gagliolo	[14]
13	L. Giovannacci	[1]
14	Mauro Morando	[13]
15	Giovanna Morgavi	[13]
16	Giovanni Nateri	[5]
17	Riccardo Parenti	[7]
18	Carla Penno	[7]
19	Giacomo Pruzzo	[14]
20	Luigi Raffo	[1] [6]
21	Maurizio Valle	[3] [5] [6] [7] [8] [9] [10] [11] [12]

Colors in the list of coauthors