| 2008 |
|---|
| 5 | EE | Kyuho Shim,
Youngrae Cho,
Namdo Kim,
Hyuncheol Baik,
Kyungkuk Kim,
Dusung Kim,
Jaebum Kim,
Byeongun Min,
Kyumyung Choi,
Maciej J. Ciesielski,
Seiyang Yang:
A fast two-pass HDL simulation with on-demand dump.
ASP-DAC 2008: 422-427 |
| 4 | EE | Kyuho Shim,
Kesava R. Talupuru,
Maciej J. Ciesielski,
Seiyang Yang:
Simulation Acceleration with HW Re-Compilation Avoidance.
VLSI Design 2008: 487-491 |
| 2004 |
|---|
| 3 | EE | Sungju Park,
Sangwook Cho,
Seiyang Yang,
Maciej J. Ciesielski:
A new state assignment technique for testing and low power.
DAC 2004: 510-513 |
| 1992 |
|---|
| 2 | EE | Maciej J. Ciesielski,
Seiyang Yang:
PLADE: a two-stage PLA decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 943-954 (1992) |
| 1991 |
|---|
| 1 | EE | Seiyang Yang,
Maciej J. Ciesielski:
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 4-12 (1991) |
