V. D. Agrawal

List of publications from the DBLP Bibliography Server - FAQ

2003

2 EE V. D. Agrawal: Editorial. J. Electronic Testing 19(5): 495 (2003)

1998

1 EE S. Bose, P. Agrawal, V. D. Agrawal: A rated-clock test method for path delay faults. IEEE Trans. VLSI Syst. 6(2): 323-331 (1998)

2003
2	EE	V. D. Agrawal: Editorial. J. Electronic Testing 19(5): 495 (2003)
1998
1	EE	S. Bose, P. Agrawal, V. D. Agrawal: A rated-clock test method for path delay faults. IEEE Trans. VLSI Syst. 6(2): 323-331 (1998)

Coauthor Index