| 2003 |
|---|
| 10 | EE | Hao-Yung Lo,
Hsiu-Feng Lin,
Chichyang Chen,
Jenshiuh Liu,
Chia-Cheng Liu:
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.
J. Electronic Testing 19(3): 245-269 (2003) |
| 1997 |
|---|
| 9 | | Hao-Yung Lo:
A Parallel CORDIC Algorithm for Sine and Cosine Generation.
PDPTA 1997: 713-724 |
| 8 | EE | Hao-Yung Lo:
A Uniform and Squared Direct Two's Complement Multiplier.
J. Inf. Sci. Eng. 13(1): 171-179 (1997) |
| 1996 |
|---|
| 7 | EE | Hao-Yung Lo,
Hsiu-Feng Lin,
Yue-Yuan Ho:
Logarithmic Conversion by Four Partitioned Hybrid-ROMs.
ISPAN 1996: 550-552 |
| 1995 |
|---|
| 6 | | Hao-Yung Lo,
Hsiu-Feng Lin,
Kuen-Shiuh Yang:
A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation.
ISCAS 1995: 1984-1987 |
| 1994 |
|---|
| 5 | EE | Hao-Yung Lo,
Hsiu-Feng Lin,
Chiang-Shiang Wan:
Hybrid ROM Strategy (H-ROM) for Conversion Between Binary Numbers and Logarithms.
J. Inf. Sci. Eng. 10(1): 51-69 (1994) |
| 4 | EE | Hao-Yung Lo:
An Optimal Matched and Parallel Mixed-Radix Converter.
J. Inf. Sci. Eng. 11(3): 411-421 (1994) |
| 1990 |
|---|
| 3 | | Chien-Chun Su,
Hao-Yung Lo:
An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems.
IEEE Trans. Computers 39(8): 1053-1064 (1990) |
| 1987 |
|---|
| 2 | | Hao-Yung Lo,
Jau-Ling Chen:
A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration.
IEEE Trans. Computers 36(11): 1363-1367 (1987) |
| 1985 |
|---|
| 1 | | Hao-Yung Lo,
Yoshinao Aoki:
Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array.
IEEE Trans. Computers 34(8): 681-691 (1985) |
