| 2002 |
|---|
| 10 | EE | Prasun Raha,
Scott Randall,
Richard Jennings,
Bob Helmick,
Ajith Amerasekera,
Baher Haroun:
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
ISQED 2002: 148- |
| 1995 |
|---|
| 9 | EE | Baher Haroun,
Behzad Sajjadi:
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.
FPGA 1995: 75-81 |
| 8 | | Abdelhakim Safir,
Baher Haroun,
Krishnaiyan Thulasiraman:
Floorplanning with Datapath Optimization.
ISCAS 1995: 41-44 |
| 1994 |
|---|
| 7 | | Baher Haroun,
Behzard Sajjadi:
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.
ICCD 1994: 587-589 |
| 6 | | Abdelhakim Safir,
Baher Haroun,
Krishnaiyan Thulasiraman:
A Floorplanner driven by Structural & Timing Constraints.
ISCAS 1994: 157-160 |
| 5 | | Reza Golshan,
Baher Haroun:
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems.
ISCAS 1994: 351-354 |
| 4 | | Baher Haroun,
Chao Hua Wu:
A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.
ISCAS 1994: 9-12 |
| 1992 |
|---|
| 3 | EE | F. Rouatbi,
Baher Haroun,
Asim J. Al-Khalili:
Power estimation tool for sub-micron CMOS VLSI circuits.
ICCAD 1992: 204-209 |
| 2 | | Baher Haroun,
Elie Torbey:
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.
ICCD 1992: 174-178 |
| 1989 |
|---|
| 1 | EE | Baher Haroun,
Mohamed I. Elmasry:
Architectural synthesis for DSP silicon compilers.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(4): 431-447 (1989) |
