| 2001 |
|---|
| 10 | | Alistair McEwan,
Jonathan Saul:
A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories.
The Journal of Supercomputing 19(1): 93-103 (2001) |
| 1999 |
|---|
| 9 | EE | Jonathan Saul:
Hardware/Software Codesign for FPGA-based Systems.
HICSS 1999 |
| 8 | | Alistair McEwan,
Jonathan Saul,
Andrew Bailey:
A High Speed Reconfigurable Firewall Based on Parameterization FPGA-Based Content Addressable Memories.
PDPTA 1999: 1138-1144 |
| 1997 |
|---|
| 7 | | Maurice Kilavuka Inuani,
Jonathan Saul:
Technology mapping of heterogeneous LUT-based FPGAs.
FPL 1997: 223-234 |
| 1996 |
|---|
| 6 | | Nigel Lester,
Jonathan Saul:
Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form.
FPL 1996: 185-192 |
| 1995 |
|---|
| 5 | EE | Tomasz Kozlowski,
Erik L. Dagless,
Jonathan Saul:
An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions.
ICCD 1995: 244-249 |
| 1994 |
|---|
| 4 | EE | Krzysztof Bilinski,
Erik L. Dagless,
Jonathan Saul,
Janusz Szajna:
An efficient verification algorithm for parallel controllers.
EURO-DAC 1994: 302-307 |
| 3 | | Aiguo Lu,
Jonathan Saul,
Erik L. Dagless:
Architecture Oriented Logic Optimization for Lookup Table Based FPGAs.
ICCD 1994: 26-29 |
| 1992 |
|---|
| 2 | | James Pardey,
Tomasz Kozlowski,
Jonathan Saul,
Martin Bolton:
State Assignment Algorithms for Parallel Controller Synthesis.
ICCD 1992: 316-319 |
| 1991 |
|---|
| 1 | | Jonathan Saul:
An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations.
ICCD 1991: 634-637 |
