2008 |
11 | EE | M. Yang,
L. Wang,
J. R. Tong,
A. E. A. Almaini:
Techniques for dual forms of Reed-Muller expansion conversion.
Integration 41(1): 113-122 (2008) |
2006 |
10 | EE | M. Yang,
L. Wang,
A. E. A. Almaini:
Fast Conversion for Large Canonical OR-Coincidence Functions.
APCCAS 2006: 1643-1646 |
2005 |
9 | EE | Yinshui Xia,
Lun-Yao Wang,
A. E. A. Almaini:
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
J. Comput. Sci. Technol. 20(2): 237-242 (2005) |
2004 |
8 | EE | B. Ali,
A. E. A. Almaini,
Tatiana Kalganova:
Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits.
Genetic Programming and Evolvable Machines 5(1): 11-29 (2004) |
2003 |
7 | EE | Yinshui Xia,
B. Ali,
A. E. A. Almaini:
Area and power optimization of FPRM function based circuits.
ISCAS (5) 2003: 329-332 |
6 | EE | Yinshui Xia,
Xunwei Wu,
A. E. A. Almaini:
Power Minimization of FPRM Functions Based on Polarity Conversion.
J. Comput. Sci. Technol. 18(3): 325-331 (2003) |
2002 |
5 | EE | Yinshui Xia,
A. E. A. Almaini:
Best Polarity for Low Power XOR Gate Decomposition.
DSD 2002: 53-59 |
2001 |
4 | EE | L. Wang,
A. E. A. Almaini:
Multilevel Logic Minimization Using Functional Don't Cares.
VLSI Design 2001: 417-424 |
3 | EE | M. MacCallum,
A. E. A. Almaini:
The Application of the Wavelet Transform to Polysomnographic Signals.
WAA 2001: 284-295 |
1994 |
2 | | Z. Guan,
P. Thomson,
A. E. A. Almaini:
A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter.
ICCD 1994: 298-301 |
1978 |
1 | | A. E. A. Almaini:
Sequential Machine Implementations Using Universal Logic Modules.
IEEE Trans. Computers 27(10): 951-960 (1978) |