| 1996 |
|---|
| 5 | | Hungse Cha,
Elizabeth M. Rudnick,
Janak H. Patel,
Ravishankar K. Iyer,
Gwan S. Choi:
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.
IEEE Trans. Computers 45(11): 1248-1256 (1996) |
| 1994 |
|---|
| 4 | EE | Abhijit Dharchoudhury,
Sung-Mo Kang,
Hungse Cha,
Janak H. Patel:
Fast timing simulation of transient faults in digital circuits.
ICCAD 1994: 719-722 |
| 3 | | Hungse Cha,
Janak H. Patel:
Latch Design for Transient Pulse Tolerance.
ICCD 1994: 385-388 |
| 1993 |
|---|
| 2 | | Hungse Cha,
Elizabeth M. Rudnick,
Gwan S. Choi,
Janak H. Patel,
Ravishankar K. Iyer:
A Fast and Accurate Gate-Level Transient Fault Simulation Environment.
FTCS 1993: 310-319 |
| 1 | | Hungse Cha,
Janak H. Patel:
A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits.
ICCD 1993: 538-542 |
