William A. Rogers

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15EESanghyeon Baeg, William A. Rogers: A cost-effective design for testability: clock line control and test generation using selective clocking. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 850-861 (1999)
14 Sanghyeon Baeg, William A. Rogers: A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. ICCD 1994: 354-358
13 Sanghyeon Baeg, William A. Rogers: Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. ITC 1994: 340-349
12EEHyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers: Hierarchical test pattern generation: a cost model and implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1029-1039 (1993)
11 Mark A. Heap, William A. Rogers, M. Ray Mercer: A Synthesis Algorithm for Two-Level XOR Based Circuits. ICCD 1992: 459-463
10EEHyoung B. Min, William A. Rogers: A test methodology for finite state machines using partial scan design. J. Electronic Testing 3(2): 127-137 (1992)
9 Mark D. Sloan, William A. Rogers, Srihari Shoroff: The Impedance Fault Model and Design for Robust Impedance Fault Testability. ICCAD 1991: 504-507
8EEHyoung B. Min, William A. Rogers: Search strategy switching: A cost model and an analysis of backtracking. J. Electronic Testing 1(2): 125-137 (1990)
7 Hyoung B. Min, William A. Rogers: Search Strategy Switching: An Alternative to Increased Backtracking. ITC 1989: 803-811
6 Mark A. Heap, William A. Rogers: Generating Single-Sstuck-Fault Coverage from a Collapsed-Fault Set. IEEE Computer 22(4): 51-57 (1989)
5EEPatrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers: Fault Simulation in a Distributed Environment. DAC 1988: 686-691
4EEWilliam A. Rogers, John F. Guzolek, Jacob A. Abraham: Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 848-862 (1987)
3 Hongtao P. Chang, William A. Rogers, Jacob A. Abraham: Structured Functional Level Test Generation Using Binary Decision Diagrams. ITC 1986: 97-104
2EEWilliam A. Rogers, Jacob A. Abraham: High level hierarchical fault simulation techniques. ACM Conference on Computer Science 1985: 89-97
1 William A. Rogers, Jacob A. Abraham: CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. ITC 1985: 710-716

Coauthor Index

1Jacob A. Abraham [1] [2] [3] [4] [5]
2Sanghyeon Baeg [13] [14] [15]
3Hongtao P. Chang [3]
4Patrick A. Duba [5]
5John F. Guzolek [4]
6Mark A. Heap [6] [11]
7Hwei-Tsu Ann Luh [12]
8M. Ray Mercer [11]
9Hyoung B. Min [7] [8] [10] [12]
10Rabindra K. Roy [5]
11Srihari Shoroff [9]
12Mark D. Sloan [9]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)