1999 |
15 | EE | Sanghyeon Baeg,
William A. Rogers:
A cost-effective design for testability: clock line control and test generation using selective clocking.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 850-861 (1999) |
1994 |
14 | | Sanghyeon Baeg,
William A. Rogers:
A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.
ICCD 1994: 354-358 |
13 | | Sanghyeon Baeg,
William A. Rogers:
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation.
ITC 1994: 340-349 |
1993 |
12 | EE | Hyoung B. Min,
Hwei-Tsu Ann Luh,
William A. Rogers:
Hierarchical test pattern generation: a cost model and implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1029-1039 (1993) |
1992 |
11 | | Mark A. Heap,
William A. Rogers,
M. Ray Mercer:
A Synthesis Algorithm for Two-Level XOR Based Circuits.
ICCD 1992: 459-463 |
10 | EE | Hyoung B. Min,
William A. Rogers:
A test methodology for finite state machines using partial scan design.
J. Electronic Testing 3(2): 127-137 (1992) |
1991 |
9 | | Mark D. Sloan,
William A. Rogers,
Srihari Shoroff:
The Impedance Fault Model and Design for Robust Impedance Fault Testability.
ICCAD 1991: 504-507 |
1990 |
8 | EE | Hyoung B. Min,
William A. Rogers:
Search strategy switching: A cost model and an analysis of backtracking.
J. Electronic Testing 1(2): 125-137 (1990) |
1989 |
7 | | Hyoung B. Min,
William A. Rogers:
Search Strategy Switching: An Alternative to Increased Backtracking.
ITC 1989: 803-811 |
6 | | Mark A. Heap,
William A. Rogers:
Generating Single-Sstuck-Fault Coverage from a Collapsed-Fault Set.
IEEE Computer 22(4): 51-57 (1989) |
1988 |
5 | EE | Patrick A. Duba,
Rabindra K. Roy,
Jacob A. Abraham,
William A. Rogers:
Fault Simulation in a Distributed Environment.
DAC 1988: 686-691 |
1987 |
4 | EE | William A. Rogers,
John F. Guzolek,
Jacob A. Abraham:
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 848-862 (1987) |
1986 |
3 | | Hongtao P. Chang,
William A. Rogers,
Jacob A. Abraham:
Structured Functional Level Test Generation Using Binary Decision Diagrams.
ITC 1986: 97-104 |
1985 |
2 | EE | William A. Rogers,
Jacob A. Abraham:
High level hierarchical fault simulation techniques.
ACM Conference on Computer Science 1985: 89-97 |
1 | | William A. Rogers,
Jacob A. Abraham:
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
ITC 1985: 710-716 |