| 2007 |
| 25 | EE | Fabrice Monteiro,
Stanislaw J. Piestrak,
Houssein Jaber,
Abbas Dandache:
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.
IOLTS 2007: 199-200 |
| 2006 |
| 24 | EE | Damien Leroy,
Stanislaw J. Piestrak,
Fabrice Monteiro,
Abbas Dandache,
Stéphane Rossignol,
Pascal Moitrel:
Characterizing Laser-Induced Pulses in ICs: Methodology and Results.
IOLTS 2006: 11-16 |
| 2005 |
| 23 | EE | Damien Leroy,
Stanislaw J. Piestrak,
Fabrice Monteiro,
Abbas Dandache:
Modeling of Transients Caused by a Laser Attack on Smart Cards.
IOLTS 2005: 193-194 |
| 2003 |
| 22 | EE | Stanislaw J. Piestrak,
Abbas Dandache,
Fabrice Monteiro:
Designing fault-secure parallel encoders for systematic linear error correcting codes.
IEEE Transactions on Reliability 52(4): 492-500 (2003) |
| 2002 |
| 21 | EE | Stanislaw J. Piestrak:
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage.
DFT 2002: 354-364 |
| 20 | EE | Stanislaw J. Piestrak:
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.
IEEE Trans. Computers 51(2): 229-234 (2002) |
| 19 | EE | Stanislaw J. Piestrak:
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'.
IEEE Trans. Computers 51(6): 735-736 (2002) |
| 2001 |
| 18 | EE | Stanislaw J. Piestrak,
Abbas Dandache,
Fabrice Monteiro:
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.
DFT 2001: 314- |
| 17 | EE | Stanislaw J. Piestrak,
Dimitris Bakalis,
Xrysovalantis Kavousianos:
On the Design of Self-Testing Checkers for Modified Berger Codes.
IOLTW 2001: 153-157 |
| 1999 |
| 16 | EE | Jerzy W. Greblicki,
Stanislaw J. Piestrak:
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits.
EDCC 1999: 251-266 |
| 1998 |
| 15 | EE | Stanislaw J. Piestrak:
Membership Test Logic for Delay-Insensitive Codes.
ASYNC 1998: 194- |
| 14 | EE | Stanislaw J. Piestrak:
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.
J. Electronic Testing 12(1-2): 63-68 (1998) |
| 1997 |
| 13 | EE | Stanislaw J. Piestrak:
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes.
DFT 1997: 119-127 |
| 1996 |
| 12 | EE | Stanislaw J. Piestrak:
Self-Checking Design in Eastern Europe.
IEEE Design & Test of Computers 13(1): 16-25 (1996) |
| 11 | | Stanislaw J. Piestrak:
Design of Self-Testing Checkers for Borden Codes.
IEEE Trans. Computers 45(4): 461-469 (1996) |
| 10 | EE | Stanislaw J. Piestrak:
Design of minimal-level PLA self-testing checkers for m-out-of-n codes.
IEEE Trans. VLSI Syst. 4(2): 264-272 (1996) |
| 1995 |
| 9 | | Stanislaw J. Piestrak,
Takashi Nanya:
Towards Totally Self-Checking Delay-Insensitive Systems.
FTCS 1995: 228-237 |
| 1994 |
| 8 | | Stanislaw J. Piestrak:
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes.
ICCD 1994: 128-131 |
| 7 | | Stanislaw J. Piestrak:
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem.
ICCD 1994: 508-511 |
| 6 | | Stanislaw J. Piestrak:
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.
IEEE Trans. Computers 43(1): 68-77 (1994) |
| 1993 |
| 5 | | Stanislaw J. Piestrak:
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.
IEEE Trans. Computers 42(6): 700-712 (1993) |
| 1991 |
| 4 | | Stanislaw J. Piestrak:
Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes.
Fault-Tolerant Computing Systems 1991: 181-192 |
| 3 | | Stanislaw J. Piestrak:
Design of a Self-Testing Checker for Borden Code.
ICCD 1991: 582-585 |
| 1990 |
| 2 | | Stanislaw J. Piestrak:
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.
IEEE Trans. Computers 39(3): 360-374 (1990) |
| 1987 |
| 1 | | Stanislaw J. Piestrak:
Design of Fast Self-Testing Checkers for a Class of Berger Codes.
IEEE Trans. Computers 36(5): 629-634 (1987) |