| 2006 |
|---|
| 8 | EE | Atsushi Konno,
Ryo Uchikura,
Toshiyuki Ishihara,
Teppei Tsujita,
Takeaki Sugimura,
Jun Deguchi,
Mitsumasa Koyanagi,
Masaru Uchiyama:
Development of a High Speed Vision System for Mobile Robots.
IROS 2006: 1372-1377 |
| 2005 |
|---|
| 7 | | Takeaki Sugimura,
Yuta Konishi,
Yoshihiro Nakatani,
Takafumi Fukushima,
Hiroyuki Kurino,
Mitsumasa Koyanagi:
Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure.
ARCS Workshops 2005: 27-32 |
| 2004 |
|---|
| 6 | EE | Zhe Liu,
JeoungChill Shim,
Hiroyuki Kurino,
Mitsumasa Koyanagi:
Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory.
AINA (2) 2004: 241-244 |
| 5 | EE | Zhe Liu,
JeoungChill Shim,
Hiroyuki Kurino,
Mitsumasa Koyanagi:
Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip.
PDCAT 2004: 564-569 |
| 2002 |
|---|
| 4 | EE | Robert W. Brodersen,
Anthony M. Hill,
John Kibarian,
Desmond Kirkpatrick,
Mark A. Lavin,
Mitsumasa Koyanagi:
Nanometer design: what hurts next...?
DAC 2002: 242 |
| 2000 |
|---|
| 3 | | Hiroyuki Kurino,
M. Nakagawa,
Kang Wook Lee,
Tomonori Nakamura,
Yuusuke Yamada,
Ki Tae Park,
Mitsumasa Koyanagi:
Smart Vision Chip Fabricated Using Three Dimensional Integration Technology.
NIPS 2000: 720-726 |
| 1998 |
|---|
| 2 | | K. Hirano,
T. Ono,
Hiroyuki Kurino,
Mitsumasa Koyanagi:
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory.
ASP-DAC 1998: 333-334 |
| 1991 |
|---|
| 1 | | Mitsumasa Koyanagi:
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections.
VLSI 1991: 377-386 |
