| 2007 |
|---|
| 16 | EE | Shoji Kawahito:
CMOS Imaging Devices for New Markets of Vision Systems.
IEICE Transactions 90-C(10): 1858-1868 (2007) |
| 2006 |
|---|
| 15 | EE | Kazutaka Honda,
Masanori Furuta,
Shoji Kawahito:
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues.
ISCAS 2006: 1031-1034 |
| 14 | EE | Shoji Kawahito:
Circuit and Device Technologies for CMOS functional Image Sensors.
VLSI-SoC 2006: 42-47 |
| 13 | EE | Masayuki Uno,
Shoji Kawahito:
Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit.
IEICE Transactions 89-C(6): 702-709 (2006) |
| 12 | EE | Zheng Liu,
Masanori Furuta,
Shoji Kawahito:
Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits.
IEICE Transactions 89-C(6): 710-716 (2006) |
| 2005 |
|---|
| 11 | EE | Shoji Kawahito,
Kazutaka Honda,
Masanori Furuta,
Nobuhiro Kawai,
Daisuke Miyazaki:
Low-Power Design of High-Speed A/D Converters.
IEICE Transactions 88-C(4): 468-478 (2005) |
| 10 | EE | Hiroto Yasuura,
Shoji Kawahito:
Special Section on Papers Selected from AP-ASIC 2004.
IEICE Transactions 88-C(8): 1704 (2005) |
| 2003 |
|---|
| 9 | EE | Atsushi Suzuki,
Shoji Kawahito,
Daisuke Miyazaki,
Masanori Furuta:
A digitally skew correctable multi-phase clock generator using a master-slave DLL.
ISCAS (1) 2003: 105-108 |
| 2002 |
|---|
| 8 | | Dwi Handoko,
Shoji Kawahito,
Yoshiaki Tadokoro,
Akira Matsuzawa:
Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor.
IEEE Trans. Circuits Syst. Video Techn. 12(12): 1084- (2002) |
| 1998 |
|---|
| 7 | | Shoji Kawahito,
Makoto Yoshida,
Masaaki Sasaki,
Daisuke Miyazaki,
Yoshiaki Tadokoro,
Kenji Murata,
Shiro Doushou,
Akira Matsuzawa:
A CMOS Smart Image Sensor LSI for Focal-Plane Compression.
ASP-DAC 1998: 339-340 |
| 6 | | Shoji Kawahito,
Yoshiaki Tadokoro,
Akira Matsuzawa:
CMOS Image Sensors with Video Compression.
ASP-DAC 1998: 595-600 |
| 1996 |
|---|
| 5 | | Shoji Kawahito,
Makoto Ishida,
Tasuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
Author's Reply.
IEEE Trans. Computers 45(5): 639 (1996) |
| 1994 |
|---|
| 4 | | Shoji Kawahito,
Makoto Ishida,
Tetsuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers 43(1): 34-42 (1994) |
| 1992 |
|---|
| 3 | | Shoji Kawahito,
Y. Mitsui,
Makoto Ishida,
Tetsuro Nakamura:
Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI.
ISMVL 1992: 337-345 |
| 1991 |
|---|
| 2 | | Shoji Kawahito,
K. Mizuno,
Tasuro Nakamura:
Multiple-Valued Current-Mode Arithmetic Circuits Based on Redundant Positive-Digit Number Representations.
ISMVL 1991: 330-339 |
| 1988 |
|---|
| 1 | | Michitaka Kameyama,
Shoji Kawahito,
Tatsuo Higuchi:
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.
IEEE Computer 21(4): 43-56 (1988) |
