| 2001 |
|---|
| 4 | EE | Motokazu Ozawa,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya,
Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
ASYNC 2001: 162-172 |
| 1998 |
|---|
| 3 | | Akihiro Takamura,
Motokazu Ozawa,
Izumi Fukasaku,
Taro Fujii,
Yoichiro Ueno,
Masashi Imai,
Masashi Kuwako,
Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor.
ASP-DAC 1998: 319-320 |
| 1997 |
|---|
| 2 | | Akihiro Takamura,
Masashi Kuwako,
Masashi Imai,
Taro Fujii,
Motokazu Ozawa,
Izumi Fukasaku,
Yoichiro Ueno,
Takashi Nanya:
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.
ICCD 1997: 288-294 |
| 1994 |
|---|
| 1 | EE | Takashi Nanya,
Yoichiro Ueno,
Hiroto Kagotani,
Masashi Kuwako,
Akihiro Takamura:
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor.
IEEE Design & Test of Computers 11(2): 50-63 (1994) |
