| 2002 |
|---|
| 11 | | Hao-Chieh Chang,
Yung-Chi Chang,
Yi-Chu Wang,
Wei-Ming Chao,
Liang-Gee Chen:
VLSI architecture design of MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Techn. 12(9): 741- (2002) |
| 2001 |
|---|
| 10 | EE | Chung-Jr Lian,
Liang-Gee Chen,
Hao-Chieh Chang,
Yung-Chi Chang:
Design and implementation of JPEG encoder IP core.
ASP-DAC 2001: 29-30 |
| 9 | EE | Yung-Chi Chang,
Chao-Chih Huang,
Hao-Chieh Chang,
Hung-Chi Fang,
Liang-Gee Chen:
Error-Propagation Analysis and Concealment Strategy for MPEG-4 Video Bitstream with Data Partitioning.
ICME 2001 |
| 8 | EE | Hao-Chieh Chang,
Zhong-Lan Yang,
Chung-Jr Lian,
Liang-Gee Chen:
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding.
ISCAS (2) 2001: 193-196 |
| 7 | EE | Mei-Yun Hsu,
Hao-Chieh Chang,
Yi-Chu Wang,
Liang-Gee Chen:
Scalable module-based architecture for MPEG-4 BMA motion estimation.
ISCAS (2) 2001: 245-248 |
| 6 | | Yi-Chu Wang,
Hao-Chieh Chang,
Wei-Ming Chao,
Liang-Gee Chen:
Efficient architecture of binary motion estimation for MPEG-4 shape coding.
VCIP 2001: 959-967 |
| 2000 |
|---|
| 5 | EE | Hao-Chieh Chang,
Jiun-Ying Jiu,
Li-Lin Chen,
Liang-Gee Chen:
A Low Power 8 x 8 Direct 2-D DCT Chip Design.
VLSI Signal Processing 26(3): 319-332 (2000) |
| 1999 |
|---|
| 4 | EE | Sheng-Chieh Huang,
Liang-Gee Chen,
Hao-Chieh Chang:
A novel image compression algorithm by using Log-Exp transform.
ISCAS (4) 1999: 17-20 |
| 3 | EE | Jun-Fu Shen,
Liang-Gee Chen,
Hao-Chieh Chang,
Tu-Chih Wang:
Low power full-search block-matching motion estimation chip for H.263+.
ISCAS (4) 1999: 299-302 |
| 2 | EE | Hao-Chieh Chang,
Liang-Gee Chen,
Yung-Chi Chang,
Sheng-Chieh Huang:
A VLSI architecture design of VLC encoder for high data rate video/image coding.
ISCAS (4) 1999: 398-401 |
| 1998 |
|---|
| 1 | | Liang-Gee Chen,
Juing-Ying Jiu,
Hao-Chieh Chang,
Yung-Pin Lee,
Chung-Wei Ku:
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm.
ASP-DAC 1998: 145-150 |
