| 2005 |
|---|
| 4 | EE | Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Yasuki Tanabe,
Toshihiro Hanawa,
Hideharu Amano:
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).
Parallel Computing 31(3-4): 352-370 (2005) |
| 2004 |
|---|
| 3 | | Masato Sumiyoshi,
Takashi Midorikawa,
Yasuki Tanabe,
Hideharu Amano:
Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory.
ISCA PDCS 2004: 296-301 |
| 2003 |
|---|
| 2 | | Yasuki Tanabe,
Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Toshihiro Hanawa,
Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.
PDPTA 2003: 1148-1154 |
| 1998 |
|---|
| 1 | | Takashi Midorikawa,
Takayuki Kamei,
Toshihiro Hanawa,
Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
ASP-DAC 1998: 337-338 |
