2007 | ||
---|---|---|
36 | EE | Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura: Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation. IEICE Transactions 90-D(3): 627-636 (2007) |
2006 | ||
35 | EE | Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba: Ray Tracing Hardware System Using Plane-Sphere Intersections. FPL 2006: 1-6 |
2005 | ||
34 | Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura: An Operand Status Based Instruction Steering Scheme for Clustered Architectures. CDES 2005: 168-174 | |
33 | EE | Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura: Cooperation of Neighboring PEs in Clustered Architectures. SBAC-PAD 2005: 134-142 |
32 | EE | Takeshi Miura, Kentaro Sano, Ken-ichi Suzuki, Tadao Nakamura: A Competitive Learning Algorithm with Controlling Maximum Distortion. JACIII 9(2): 166-174 (2005) |
2004 | ||
31 | EE | Shintaro Momose, Kentaro Sano, K. Suzuki, Tadao Nakamura: Parallel competitive learning algorithm for fast codebook design on partitioned space. CLUSTER 2004: 449-457 |
30 | EE | Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura: A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. ITCC (1) 2004: 572-578 |
29 | EE | Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura: Efficient parallel processing of competitive learning algorithms. Parallel Computing 30(12): 1361-1383 (2004) |
28 | EE | Kentaro Sano, Yusuke Kobayashi, Tadao Nakamura: Differential coding scheme for efficient parallel image composition on a PC cluster system. Parallel Computing 30(2): 285-299 (2004) |
2003 | ||
27 | EE | Tadao Nakamura: Toward Architecting and Designing Novel Computers. Asia-Pacific Computer Systems Architecture Conference 2003: 8-13 |
2002 | ||
26 | Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Taira Nakajima, C. D. Lima, Hiroaki Kobayashi, Tadao Nakamura: Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. IASTED PDCS 2002: 578-582 | |
25 | C. D. Lima, Kentaro Sano, Tadao Nakamura: Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. IASTED PDCS 2002: 718-723 | |
24 | EE | Tomoyuki Nagase, Takashi Araki, Yoshio Yoshioka, Tadao Nakamura: Moderating traffic flow over conventional ATM service. ISCC 2002: 659-663 |
2001 | ||
23 | Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura: 3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. ICCD 2001: 462-467 | |
22 | EE | Emad Rashid, Takashi Araki, Tadao Nakamura: An Active Network for Improving Performance of Traffic Flow over Conventional ATM Service. ICN (2) 2001: 620-627 |
21 | EE | Emad Rashid, Yoshio Yoshioka, Takashi Araki, Tadao Nakamura: Variable-Length Coding based on Bent Sequences for W.ireless Advertising. ISCC 2001: 568-572 |
20 | EE | Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura: Scaling Up Of Wave Pipelines. VLSI Design 2001: 439-445 |
2000 | ||
19 | EE | Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura: Reconfigurable synchronized dataflow processor. ASP-DAC 2000: 27-28 |
18 | EE | Tadao Nakamura: Cool Chips III. IEEE Micro 20(6): 83-84 (2000) |
1999 | ||
17 | EE | Ken-ichi Suzuki, Nobuyuki Oba, Shigenori Shimizu, Hiroaki Kobayashi, Tadao Nakamura: Time stamp invalidation of TLB-unified cache and its performance evaluation. Systems and Computers in Japan 30(11): 94-106 (1999) |
16 | EE | Takuya Nakaike, Takehito Sasaki, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura: A scheduling method for instruction-level parallel processing of vectorand scalar instructions. Systems and Computers in Japan 30(13): 23-33 (1999) |
1998 | ||
15 | Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura: Automated Design of Wave Pipelined Multiport Register Files. ASP-DAC 1998: 197-202 | |
1997 | ||
14 | EE | Jie Hu, Tadao Nakamura, Lei Li: Convergence, Complexity and Simulation of Monotone Asynchronous Iterative Method for Computing Fixed Point on a Distributed Computer. Parallel Algorithms Appl. 11(1-2): 1-11 (1997) |
13 | EE | Jie Hu, Tadao Nakamura, Lei Li: Asynchronous Monotone Newton Iterative Method on Distributed Computers. Parallel Algorithms Appl. 12(4): 341-348 (1997) |
12 | EE | Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura: Decoupled modified-bit cache. Systems and Computers in Japan 28(6): 49-59 (1997) |
1996 | ||
11 | EE | Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, Tadao Nakamura: A Hierarchical Parallel Processing System for the Multipass-Rendering Method. IPPS 1996: 62-67 |
1995 | ||
10 | Jie Hu, Tadao Nakamura, Lei Li: The Convergence of Asynchronous Monotone Newton Iterations on Distributed Computer. PPSC 1995: 106-107 | |
9 | EE | Jie Hu, Lei Li, Tadao Nakamura: A Divide-and-inner Product Parallel Algorithm for Polynomial Evaluation. Parallel Algorithms Appl. 6(1): 63-66 (1995) |
8 | EE | Lei Li, Tadao Nakamura: The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator. Parallel Algorithms Appl. 7(3-4): 229-235 (1995) |
1993 | ||
7 | Masa-Aki Fukase, Tadao Nakamura: Parallel Processing and Hardware Support of Symbols. ICTAI 1993: 450-451 | |
6 | Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura: An Adaptive Network Routing Method by Electrical-Circuit Modeling. INFOCOM 1993: 586-592 | |
1988 | ||
5 | Hiroaki Kobayashi, Satoshi Nishimura, Hideyuki Kubota, Tadao Nakamura, Yoshiharu Shigei: Load balancing strategies for a parallel ray-tracing system based on constant subdivision. The Visual Computer 4(4): 197-209 (1988) | |
1987 | ||
4 | Hiroaki Kobayashi, Tadao Nakamura, Yoshiharu Shigei: Parallel processing of an object space for image synthesis using ray tracing. The Visual Computer 3(1): 13-22 (1987) | |
1984 | ||
3 | Tadao Nakamura, Hiroaki Kobayashi, Jun Miyajima, Noboru Endo, Yoshiharu Shigei: A Language Processor of an Intelligent Link System. ICC (2) 1984: 527-530 | |
2 | Kuninobu Tanno, Tadao Nakamura, Risaburo Sato: An Analysis of the Receiving Behaviour of a Window Flow Control Mechanism in Packet Switching Networks. ICC (3) 1984: 1331-1334 | |
1981 | ||
1 | Makoto Hasegawa, Tadao Nakamura, Yoshiharu Shigei: Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. ISCA 1981: 367-372 |