2007 | ||
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3 | EE | Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno: Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. IEICE Transactions 90-C(4): 848-855 (2007) |
1998 | ||
2 | Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi: A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs. ASP-DAC 1998: 51-56 | |
1990 | ||
1 | Masahiro Tomita, Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi: An Algorithm for Locating Logic Design Errors. ICCAD 1990: 468-471 |
1 | Masato Edahiro | [2] |
2 | Hironori Imura | [3] |
3 | Hong-Hai Jiang | [1] |
4 | Yumi Kakuhara | [3] |
5 | Naoyoshi Kawahara | [3] |
6 | Hiroyuki Kunishima | [3] |
7 | Noriaki Oda | [3] |
8 | Sadayuki Ohnishi | [3] |
9 | Makoto Sekine | [3] |
10 | Shuji Sone | [3] |
11 | Masayoshi Tagami | [3] |
12 | Shuji Takahashi | [2] |
13 | Masahiro Tomita | [1] |
14 | Kazuyoshi Ueno | [3] |
15 | Kenta Yamada | [3] |
16 | Tamotsu Yamamoto | [1] |